Design Optimization for Integrated Neural Recording Systems

Chae, Moo Sung; Liu, Wentai; Sivaprakasam, Mohanasankar

doi:10.1109/jssc.2008.2001877

Cited by 107 publications

(49 citation statements)

References 11 publications

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“…From the second to the fourth operating conditions, the large THD and the small ENOB values are due to the dissatisfaction of the sampling condition (and the payloads of the Hardware Trojans). Due to the fact that an analog to digital converter forms a nearly small portion of the overall power consumption and area occupation of a system on chip [41][42][43][44][45], the area and power overheads made by the Trojan and defense circuits are relatively low. Meanwhile, the delays caused by the datapath-based Trojan and defense circuits are around 0.2 ns and 403 ns, respectively, in this simulation analysis.…”

Section: Resultsmentioning

confidence: 99%

Security Interrogation and Defense for SAR Analog to Digital Converter

2017

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Nowadays, the analog and mixed-signal intellectual property (IP) cores play an important role in system on chip (SoC) design due to their capabilities in performing critical functions. These IPs can be the target of adversaries similar to their digital counterparts. In this work, we study the security aspects of a tunnel field effect transistor (TFET)-based six-bit successive approximation register (SAR) analog to digital converter (ADC) through proposing two threats and two countermeasures that target the output signals of the ADC datapath and its control unit. The datapath-based threat manipulates the exiting signals from the register file, and its countermeasure attempts to filter the ADC output based on the convention of having ±1 least significant bit variation (at maximum) between the adjacent sampled data points. The control-based threat manipulates the exiting signals from the control unit, and its countermeasure is a trustworthy replication of a part of the ADC circuit that is used to provide reference data for security examination and output filtering.

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Section: Resultsmentioning

confidence: 99%

Security Interrogation and Defense for SAR Analog to Digital Converter

2017

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“…The same concept may be applied for the defense hardware implementation. Meanwhile, it is assumed that the contribution of the defense hardware to the total chip area, performance, and power consumption will not be significant, considering all the blocks in the ∆Σ ADC (not only the modulator) along with the nearly small portion that it occupies in a system-on-chip design [25,26].…”

Section: Threat Models and Countermeasures For A Delta-sigma Adcmentioning

confidence: 99%

Mixed-Signal Hardware Security: Attacks and Countermeasures for ΔΣ ADC

Taheri

Yuan

2017

Electronics

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Mixed-signal integrated circuits (ICs) play an eminent and critical role in design and development of the embedded systems leveraged within smart weapons and military systems. These ICs can be a golden target for adversaries to compromise in order to function maliciously. In this work, we study the security aspects of a tunnel field effect transistor (TFET)-based first-order one-bit delta-sigma (∆Σ) analog to digital converter (ADC) through proposing four attack and one defense models. The first attack manipulates the input signal to the ∆Σ modulator. The second attack manipulates the analog version of the modulator output bit and is triggered by the noise signal. The third attack manipulates the modulator output bit and has a controllable trigger mechanism. The fourth attack manipulates the analog version of the modulator output bit and is triggered by a victim capacitance within the chip. For the defense, a number of signal processing filters are used in order to purge the analog version of the modulator output bit for elimination of the malicious unwanted features, introduced by the attacks. According to the simulation results, the second threat model displays the strongest attack. Derived from the countermeasure evaluation, the best filter to confront the threat models is the robust regression using the least absolute residual computing method.

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“…A practical approach is to find the optimal number of channels per ADC so as to obtain a better trade-off between power and area. For the targeted 64-channel system, 16 channels are shared by one ADC, to achieve the minimum power-area product for the entire system [22]. Without utilizing a variable-gain amplifier as in many conventional ECoG systems, such as [23], a 80 dB dynamic range (DR) is typically required for the ADC to resolve ECoG signals [24].…”

Section: System Architecture and Adc Specificationsmentioning

confidence: 99%

A Power-Efficient Continuous-Time Incremental Sigma-Delta ADC for Neural Recording Systems

Tao

Rusu

2015

IEEE Trans. Circuits Syst. I

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Abstract-This paper presents an analog-to-digital converter (ADC) dedicated to neural recording systems. By using two continuous-time incremental sigma-delta ADCs in a pipeline configuration, the proposed ADC can achieve high-resolution without sacrificing the conversion rate. This two-step architecture is also power-efficient, as the resolution requirement for the incremental sigma-delta ADC in each step is significantly relaxed. To further enhance the power efficiency, a class-AB output stage and a dynamic summing comparator are used to implement the sigma-delta modulators. A prototype chip, designed and fabricated in a standard 0.18 µm CMOS process, validates the proposed ADC architecture. Measurement results show that the ADC achieves a peak signal-to-noise-plus-distortion ratio of 75.9 dB over a 4 kHz bandwidth; the power consumption is 34.8 µW, which corresponds to a figure-of-merit of 0.85 pJ/conv.

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Design Optimization for Integrated Neural Recording Systems

Cited by 107 publications

References 11 publications

Security Interrogation and Defense for SAR Analog to Digital Converter

Security Interrogation and Defense for SAR Analog to Digital Converter

Mixed-Signal Hardware Security: Attacks and Countermeasures for ΔΣ ADC

A Power-Efficient Continuous-Time Incremental Sigma-Delta ADC for Neural Recording Systems

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