Design Optimization of High-Speed and Low-Power Operational Transconductance Amplifier Using gm/ID Lookup Table Methodology

Konishi, Tadataka; Inazu, Kenji; Lee, Jun Gyu; Natsui, Masanori; Masui, Shoichi; Murmann, Boris

doi:10.1587/transele.e94.c.334

Cited by 32 publications

(16 citation statements)

References 8 publications

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“…This result is similar to that of the CS stage given by (11); only the term involving the inversion level differs. The HD 3 of the differential pair is 6 dB better that that of the CS stage in weak inversion.…”

Section: B Differential Pairsupporting

confidence: 83%

“…For each case, we find the required q using (16), and then compute g m /I D from (6). Once g m /I D is determined, the current density I D /W is also fixed and can be found from pre-computed charts or look-up tables [11]. Finally, the absolute width and tail current follow from the required transconductance, set by the noise requirement or the voltage gain A v and load resistance R L (we assumed A v = 2, R L = 200 Ω).…”

Section: B Differential Pairmentioning

confidence: 99%

“…In the simplest case, the only parameter needed is the transistor's subthreshold slope factor (n), which is a well-understood and bounded quantity. Key to this simplification is that the operating point is defined and expressed via the transconductance-to-current ratio (g m /I D ), a quantity that is also useful in the context of general circuit sizing [9]- [11]. In [6], g m /I D was used to define the operating point, but no analytical relationship to the distortion parameters was established.…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Calculation of MOSFET distortion using the transconductance-to-current ratio (g<inf>m</inf>/I<inf>D</inf>)

Jespers

Murmann

2015

2015 IEEE International Symposium on Circuits and Systems (ISCAS)

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We present analytical expressions for MOSFET distortion as a function of inversion level, represented by g m /I D as a proxy. The expressions are particularly useful for moderate inversion, where the generic textbook equations fail. Unlike previous approaches, the method requires only a small number of technology parameters. For an estimation of g m nonlinearity, only the subthreshold slope is needed. Two additional parameters are required to model g ds nonlinearity. The derived expressions are validated based on SPICE simulations using a well-calibrated 65-nm PSP model set.

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Section: B Differential Pairsupporting

confidence: 83%

Section: B Differential Pairmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Calculation of MOSFET distortion using the transconductance-to-current ratio (g<inf>m</inf>/I<inf>D</inf>)

Jespers

Murmann

2015

2015 IEEE International Symposium on Circuits and Systems (ISCAS)

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“…The last step for the current design iteration is to update the initial state of V DS1a, b and V DS4a . b consistent with expressions (18) and (19):…”

Section: Design Of a Low-voltage Folded-cascode Otasupporting

confidence: 76%

“…The present g m /I D methodologies do not, conventionally, take into account the effect of the gate channel width on the main design variables such as g m /I D and g m /g O[8,[17][18][19]21]. Instead, the results from current density I D /W are used to calculate W when g m /I D and I D are specified a priori as a function of L. Simulation results show that the dependence of such parameters upon W is not negligible when the gate size of the nano-scale devices is reduced below 1 to 2 µm.Fig.…”

mentioning

confidence: 99%

Systematic circuit design and analysis using generalised g _m / I _D functions of MOS devices

Aminzadeh

2020

IET Circuits, Devices & Systems

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The conventional approach to implementing analogue integrated circuits in nano-scale complementary metal oxide semiconductor (CMOS) technologies relies basically on circuit simulations using the SPICE models provided by the foundries. Depending on the circuit complexity, the designer should, however, spend a significant amount of time sizing the metal oxide semiconductor field effect transistors such that maximum efficiency is achieved for minimum power consumption and silicon area. Analytical-based design procedures can assist the designer in confronting the sizing challenge of the metal oxide semiconductor (MOS) devices. The procedures are, however, dependent on circuit topology, model parameters, and device physics. This study aims at presenting a systematic approach for analysis and design of analogue circuits in scaled CMOS. For this purpose, the behaviour of short-channel MOS devices is characterised in various process and temperature corners using an updated matrix representation of different device scales, bias conditions, and small-signal parameters. The details to effectively extract the matrix derivation of the technology model files are presented, enabling to devise generalised functions for the design and analysis of the circuits. The design examples include a 0.39 V-28 µA reference circuit, and a 7.50 µA/V operationaltransconductance amplifier with 1.0 V voltage supply in 90-nm CMOS.

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Automatic generation of macromodels and design equations for application to Op Amp design

Shi

2023

Circuit Theory & Apps

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SummaryOperational amplifier (Op Amp) is a special class of analog integrated circuits. Multiple‐stage Op Amp design is of particular interest recently. However, analysis of this class of circuits has to be done manually and requires advanced skills. Automatic analysis of this class of circuits is studied in this paper, which takes a novel approach by circuit recognition and symbolic generation. Circuit recognition is deterministic, implemented by deterministic circuit partitioning and functional block extraction methods. Symbolic analysis of extracted circuit blocks can subsequently be performed with greatly reduced complexity while generated models and equations bear more useful information for circuit design. Symbolic results so generated can be applied in design space exploration, including tasks like finding the limitation in circuit topology, conducting initial sizing, and determining performance tradeoffs. This paper proposes the key algorithms for realizing the recognition of a few well‐known functional blocks frequently used in CMOS Op Amp circuits and further explores the possibility of using the recognized circuit cells in combination with the gm/ID method for circuit sizing. Preliminary tests show that this approach is a potential candidate for locating the performance boundaries of multiple‐stage Op Amps.

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Design Optimization of High-Speed and Low-Power Operational Transconductance Amplifier Using gm/ID Lookup Table Methodology

Cited by 32 publications

References 8 publications

Calculation of MOSFET distortion using the transconductance-to-current ratio (g<inf>m</inf>/I<inf>D</inf>)

Calculation of MOSFET distortion using the transconductance-to-current ratio (g<inf>m</inf>/I<inf>D</inf>)

Systematic circuit design and analysis using generalised g _m / I _D functions of MOS devices

Automatic generation of macromodels and design equations for application to Op Amp design

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Design Optimization of High-Speed and Low-Power Operational Transconductance Amplifier Using gm/ID Lookup Table Methodology

Cited by 32 publications

References 8 publications

Calculation of MOSFET distortion using the transconductance-to-current ratio (g<inf>m</inf>/I<inf>D</inf>)

Calculation of MOSFET distortion using the transconductance-to-current ratio (g<inf>m</inf>/I<inf>D</inf>)

Systematic circuit design and analysis using generalised g m / I D functions of MOS devices

Automatic generation of macromodels and design equations for application to Op Amp design

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Systematic circuit design and analysis using generalised g _m / I _D functions of MOS devices