Design Optimization of Single-/Dual-Band FET LNAs Using Noise Transformation Matrix

Hsiao, Yu-Chih; Meng, Chinchun; Yang, Chun

doi:10.1109/tmtt.2015.2508790

Cited by 12 publications

(5 citation statements)

References 23 publications

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“…For X-band applications, we propose a MBSNIM technique utilizing parasitic capacitance C gd or augmenting an additional small capacitance C GD in parallel with the CS configuration to achieve low-noise and enhanced wideband input-matching performance. ABCDparameters and Thevenin noise parameters transformed from Norton noise parameters are utilized to derive the noise performance for an inductively degenerated LNA [17]. After complicated algebraic derivations, three modified key noise parameters in the inductor-degenerated CS configuration, the transformed noise conductance G n , uncorrelated noise resistance R u , and correlated noise impedance Z c can be expressed as [17] -27…”

Section: Input-stage Analysismentioning

confidence: 99%

“…ABCDparameters and Thevenin noise parameters transformed from Norton noise parameters are utilized to derive the noise performance for an inductively degenerated LNA [17]. After complicated algebraic derivations, three modified key noise parameters in the inductor-degenerated CS configuration, the transformed noise conductance G n , uncorrelated noise resistance R u , and correlated noise impedance Z c can be expressed as [17] -27…”

Section: Input-stage Analysismentioning

confidence: 99%

“…According to Figure 2, the tedious algebraic derivation for noise parameters can turn to the equations according to noise transformation matrices in the series feedback and cascade configuration in [17,20]. The calculation process is briefly described in the Appendix.…”

Section: Input-stage Analysismentioning

confidence: 99%

“…The smallsignal equivalent circuit for calculation of i 2 o;ns is shown in Figure 5b, and the output noise current caused by source terminal can be expressed by Equation ( 13) [21]. The output correlated gate noise currents can be expressed as Equation (17). As shown in Figure 5d, the output meansquared channel noise current can be calculated as Equation (18).…”

Section: Noise Figure Calculationmentioning

confidence: 99%

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CMOS X‐band pole‐converging triple‐cascode LNA with low‐noise and wideband performance

Cao

Wang

et al. 2021

IET Circuits, Devices & Syst

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A pole-converging X-band low-noise amplifier (LNA) using 130 nm CMOS technology is proposed. An on-chip pole-converging capacitor C PC is added between the gate and drain node of the common-gate (CG) stage. The capacitor C PC combines with a noisereducing inductor L 1 to converge poles into the desired band, which results in a poleconverging effect and wideband performance. The proposed modified broadband simultaneous noise and input-matching technique is adopted in triple-cascode configuration to realize good input matching and a low noise figure (NF). Measurement results exhibit a flat maximum power gain of 17.6 dB from 8 to 12 GHz and a reverse isolation over 60 dB within the desired bandwidth along with an NF ranging from 1.5 to 3.6 dB. The LNA core dissipates 17 mW from 2.4 V supply, and the chip size occupies 1.1 � 0.9 mm 2 including all pads. The simulated and measured results show good agreement from 8 to 12 GHz.This is an open access article under the terms of the Creative Commons Attribution License, which permits use, distribution and reproduction in any medium, provided the original work is properly cited.

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Section: Input-stage Analysismentioning

confidence: 99%

Section: Input-stage Analysismentioning

confidence: 99%

Section: Input-stage Analysismentioning

confidence: 99%

Section: Noise Figure Calculationmentioning

confidence: 99%

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CMOS X‐band pole‐converging triple‐cascode LNA with low‐noise and wideband performance

Cao

Wang

et al. 2021

IET Circuits, Devices & Syst

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“…where Kr, Kg and KC are functions of Cex/Cgs [10]. And the amplifier input impedance Zin can be calculated as: ,…”

Section: A the Inductive Source Degenerated Cascode Amplifiermentioning

confidence: 99%

An Image Rejection Ku-Band CMOS Low Noise Amplifier With Bridged-Tee Band-Stop Filter

Cheng

et al. 2020

IEEE Access

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For satellite communication applications, this paper presents an image rejection Ku-band low noise amplifier (LNA) in a 65-nm CMOS process for the Hartley receiver architecture. To achieve high input/output linearity performance, the inductive source degenerated cascode and the capacitive neutralized common-source (CS) amplifier topologies are used in the LNA input and output stages, respectively. To achieve wideband input return loss, the minimum noise figure and high gain performance simultaneously, the inductive source degenerated cascode amplifier is co-designed with the fourth order input impedance matching network. For the image rejection purpose, a bridged-tee band-stop filter is proposed. The measurements show the LNA achieves 14.3-to-18.3 GHz 3 dB bandwidth with 17-to-20 dB power gain, 3.5to-4 dB noise figure, 17-to-37 dB image rejection and-5 dBm IIP3. Including all pads, the chip occupies a silicon area of 1360 × 450 μm 2 and consumes 72 mW DC power. INDEX TERMS CMOS, Ku-band, low noise amplifier (LNA), band-stop filter (BSF), image rejection.

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Design and Comparison of Wideband Cascode Low Noise Amplifier using GAA-JLFET and GAA-NC-JLFET for RFIC Applications

Raut¹,

Nanda²,

Panda³

et al. 2023

2023 3rd International Conference on Artificial Intelligence and Signal Processing (AISP)

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Design Optimization of Single-/Dual-Band FET LNAs Using Noise Transformation Matrix

Cited by 12 publications

References 23 publications

CMOS X‐band pole‐converging triple‐cascode LNA with low‐noise and wideband performance

CMOS X‐band pole‐converging triple‐cascode LNA with low‐noise and wideband performance

An Image Rejection Ku-Band CMOS Low Noise Amplifier With Bridged-Tee Band-Stop Filter

Design and Comparison of Wideband Cascode Low Noise Amplifier using GAA-JLFET and GAA-NC-JLFET for RFIC Applications

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