Design-patterning co-optimization of SRAM robustness for double patterning lithography

Abstract

Double patterning lithography (D attractive optical lithography solution for 32n technology nodes. There are two primary pitch-split double patterning (PSDP) and se patterning (SADP), which can be implemente tone or a negative tone process. Each DPL im a different impact on line space and linewidth analyzing the impact of these different DPL overall process flow can be achieved. This comprehensive analysis and optimization compares the layerwise impact of different SRAM robustness, density, and printability. I sizing optimization that accounts for increas to DPL for each layer. Experimental result industrial models show that using the best DP layer, along with the sizing optimization p achieve single exposure robustness togethe DPL printability at almost no overhead increase in write energy). Specifically, cell f can be further reduced by 5X as compar exposure failure probability, at the cost of energy by 6.3% and write delay by 2.5%.

SRAM cell performance analysis beyond 10-nm FinFET technology

“…x SADP process: For further smaller feature size, SADP process is expected for all metal layers with better line and space alignment rather than multiple LE process [2]. Process flow assumed in this paper is described in Fig.…”