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This paper describes the performance analysis of SRAM cell capability beyond 10-nm FinFET technology. Through the circuit simulation with a pseudo memory macro, optimized SRAM cell can demonstrate almost the same performance of traditional metal architecture though the read-out delay analysis. Comparing between HD (High-Density) and HC (High-Current) cell, HD cell shows better performance in the large array macro due to the less parasitic resistance and capacitance.

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The dependence of oxide chatge-to-breakdown (QBJ and device degradation on the combined post annealing of RTA and FA in the tungsten polycide gate technologv have been experimentally investigated. Based on the experimental results, QED and the degradation are improved on the lower temperature and the shorter time of RTA. Whereas E4RZ4 annealing sequence is more advantage to improve QED RI;I/FA annealing sequence is good for improving the device degradation.