Design Phase Locked Loop Accuracy towards Femtosecond Magnitude

Abstract

This paper studies the frequency synthesis for precision time protocol clock generation circuit, and more particularly focused on a multi-rate phase locked loop structure for generating an output signal at a desired frequency with reduced jitter towards the magnitude of femtosecond. We proposed a unique structured model that makes use of a multiple rate digital filter to match the noise spectrum characteristics of both input digital controlled oscillator reference and output voltage controlled oscillator respectively. The simulation for two rate case is carried out. This concept can be extended to more than two rates to match with additional noise sources' spectrum from the other devices such as fractional divider, etc.