Design procedure for settling time minimization in three-stage RNMC amplifiers

Robust design of CMOS amplifiers oriented to settling‐time specification

“…Pole-zero cancellation and tuning of phase margin (PM) or damping factor ( ) have been suggested to improve the settling time of multistage amplifiers [18,19]. Conversely, other works have exploited the closed-loop transfer function and/or numerical simulations to optimize the settling-time performance [20][21][22][23][24][25][26]. However, many of these papers provide complex relationships between the settling time and the amplifier parameters, which reduce their effective usage in a real design.…”

“…In recent years, the design of CMOS amplifiers from settling-time specifications has gained more and more attention because of the growing interest in high-performance discrete-time circuits such as precision switched-capacitor (SC) circuits, and analog-to-digital converters [18][19][20][21][22][23][24][25][26]. In the literature, the analysis has been mainly devoted to two-stage [25,26] and three-stage [18][19][20][21][22][23][24] OTAs, and different design approaches have been presented. Pole-zero cancellation and tuning of phase margin (PM) or damping factor ( ) have been suggested to improve the settling time of multistage amplifiers [18,19].…”