Design rule methodology to improve the manufacturability of the copper CMP process

Lakshminarayanan, S.; Wright, P.J.; Pallinti, J.

doi:10.1109/iitc.2002.1014900

Cited by 13 publications

(10 citation statements)

References 3 publications

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“…We considered a wide parameter space for the dimensions, as follows. Interconnect pattern density is often limited by the design rules to be in the range of 20% − 80% metal fill [11], but the probability density function for metal layers indicates that 20% − 60% is typical [12]. Thus we consider metal fill factors f in the range 0.2−0.6.…”

Section: Methodsmentioning

confidence: 99%

Simplified model for on-chip interconnects in electromagnetic modelling of System-in-Package

Holik

Drysdale

2010

2010 International Conference on Electromagnetics in Advanced Applications

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We present effective medium approximation (EMA) that provides an homogeneous equivalent for the top layer of onchip interconnects in an integrated circuit. An empirical mixing model for straightforward and fast extraction of the effective dielectric constant of a slab of integrated circuit wiring and its analytical formulation based on Maxwell-Garnett rule is presented for a range of aspect ratios, dielectric materials, metal fills, and frequencies. We expect this approach to find use in the electromagnetic modeling of System-in-Package. Experimental validation of proposed approach is demonstrated by free space measurement of a grating structure illuminated by a pair of lens horn antennas.

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Section: Methodsmentioning

confidence: 99%

Simplified model for on-chip interconnects in electromagnetic modelling of System-in-Package

Holik

Drysdale

2010

2010 International Conference on Electromagnetics in Advanced Applications

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“…Another issue to be taken into account when applying the proposed technique is the impact of dishing and erosion caused by chemical mechanical polishing (CMP) in damascene Cu lines [24], [25], [30], since sheet resistance is a function of line width and pattern density. Efficient modeling is available for mature processes [26]- [28], and the metal thickness can be controlled provided the comb-meander structure has uniform density.…”

Section: Scalability Of the Methodsmentioning

confidence: 99%

“…The resistance is assumed to be lower at the structure edge but to increase rapidly proceeding inwards. After a few tens of m from the array edge , the mean resistance of each line can be considered stabilized to the value derived from erosion [25]. A global field oxide loss is also included in the meander structure.…”

Section: Scalability Of the Methodsmentioning

confidence: 99%

Localization and Electrical Characterization of Interconnect Open Defects

Rodriguez-Montaes

Arumí

Figueras

et al. 2010

IEEE Trans. Semicond. Manufact.

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“…For example, on each metal layer, local pattern density within every predefined window must be within a specified range, for example, between 10% and 40%. These density bounds can also help in minimizing the multilayer accumulative effect, as reported in [26].…”

Section: Introductionmentioning

confidence: 94%

A Novel Wire-Density-Driven Full-Chip Routing System for CMP Variation Control

Chen

Chou²,

Wang³

et al. 2009

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Abstract-As nanometer technology advances, the post chemical-mechanical polishing (CMP) topography variation control becomes crucial for manufacturing closure. To improve the CMP quality, dummy-feature filling is typically performed by foundries after the routing stage. However, filling dummy features may greatly degrade the interconnect performance and significantly increase the input data in the following timeconsuming reticle enhancement techniques. It is, thus, desirable to consider wire-density uniformity during routing to minimize the side effects from aggressive post-layout dummy filling. In this paper, we present a new full-chip grid-based routing system considering wire density for reticle planarization enhancement. To fully consider a wire distribution, the router applies a novel two-pass top-down planarity-driven routing framework, which employs new density critical area analysis based on Voronoi diagrams and incorporates an intermediate stage of a density-driven layer/track assignment based on incremental Delaunay triangulation. Experimental results show that our methods can achieve a more balanced wire distribution than state-of-the-art works.

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Design rule methodology to improve the manufacturability of the copper CMP process

Cited by 13 publications

References 3 publications

Simplified model for on-chip interconnects in electromagnetic modelling of System-in-Package

Simplified model for on-chip interconnects in electromagnetic modelling of System-in-Package

Localization and Electrical Characterization of Interconnect Open Defects

A Novel Wire-Density-Driven Full-Chip Routing System for CMP Variation Control

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