Design rules were developed for the layout of copper Damascene interconnect layers to minimize the within-die resistance variation. The impact of various layout configurations on the metal sheet resistance was characterized using two different test vehicles. An increase in resistance was observed on wide lines and high pattern densities due to dishing and dielectric erosion, respectively. In addition to the above, narrow lines were severely impacted by the presence of wide adjacent features in close proximity. The pattern interaction distance for copper chemical-mechanical planarization (CMP) was calculated by analyzing the resistance variation at the edge of a density or width transition. In this work, the interaction distance was found to be on the order of 25 m (as opposed to a few millimeters for oxide CMP). From these results, a window of about 50 to 60 m was found to be necessary to obtain the effective pattern density for copper CMP. The resistance of the upper metal level was a strong function of the underlying layer density. Hence, multilevel pattern dependencies have to be considered when modeling and predicting the line resistance on a real design. However, unlike oxide polish, pattern density alone is insufficient to predict the final copper thickness. Width-dependent spacing rules are necessary to prevent clustering of features (narrow lines very close to wide buses) and avoid regions of very low density.

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An overview of the process performance of Stress FreePolishing technology (SFP) [I] for copper removal at sub 90nm nodes is presented in this paper. A brief description of the SFP process and polishing characteristics is provided along with electrical results. Dependence of post SFP copper surface quality on the roughness of the incoming films and post plating anneal conditions is also discussed. IntroductionCopper was introduced in the recent past by the IC industry as the material of choice for on-chip metallization. The dual Damascene scheme is used for forming the copper interconnects. Chemical mechanical planarization (CMP) is currently used for removing the copper over the field areas after the trenches and vias are filled. As the technology scales, the need to reduce on-chip capacitance has led to the use of materials with lower dielectric constants. The low mechanical strength of these films can cause delamination with traditional CMP [2]. The delamination issue may become severe with porous ultra low-k films. Removing the copper without exposing the copper-barrier interface andlor barrier-dielectric interface to traditional CMP polishing conditions can reduce the risk of damage to the dielectric film and copper lines. To address this problem, chemical enhanced planarization (CEP) and spin etch planarization (SEP) are proposed alternatives in the ITRS roadmap [3]. This paper reports results from the stress free polishing (SFP) technique, a new technology offered by ACM Research to address Cu removal without delamination when integrated with low-k

The first process integration of Cu metallization and next generation CVD ultra lowk (Trikon Orion ULK, k=2.2) is presented. The current process condition for a 130nm node Cdlowk (k=2.9) process is applied to C N L K and found to be suitable without major modifications. The comparison of post CMP measurement (dishing, erosion, peeling, and scratch) show no significant variation between control (k=2.9) and ULK. The electrical data indicates the successful integration of Cu and ULK. The interconnect capacitance is expected to reduce 20% at O.lpm technology node using the ULK film.

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