Design rules of (Mg,Zn)O-based thin-film transistors with high-κ WO3 dielectric gates

Abstract

We present a study on the design and optimization of metal-insulator-semiconductor field-effect transistors based on (Mg,Zn)O channel material with WO3 dielectric. The thickness of the dielectric and of the channel layer were adjusted independently to minimize the off-current density joff, the subthreshold slope (SS), and to modify the turn-on voltage. For optimized dielectric thickness, values of joff<10−8 A/cm2 and SS = 68 mV/decade were obtained. The variation of the (Mg,Zn)O-film thickness gives rise to a shift of the turn-on voltage: For 21 nm thick channels Von=−1.68V is obtained and by reducing the thickness to 8.6 nm Von=−0.27V. Using a Pt gate metal, normally off transistors with Von=0.19V were realized.

Low-Voltage InGaZnO Thin-Film Transistors Gated by SiO₂ Proton Conducting Films

“…The 8 nm-thick IGZO TFT exhibits a relatively lower I ON , which is not reasonable. Similarly, Lorenz et al have been reported ultra-thin (8.6 nm) (Mg, Zn)O channel TFTs have a relatively lower I ON [22] . Table 1 shows the electrical parameters of IGZO TFTs with different channel thicknesses.…”

All‐Oxide Transparent Thin‐Film Transistors Based on Amorphous Zinc Tin Oxide Fabricated at Room Temperature: Approaching the Thermodynamic Limit of the Subthreshold Swing

“…Compared to the MESFET, the gate current of the pn heterodiode is already dominating the drain current at an applied gate voltage of ≈0.5 V. This is due to the fact that metal‐oxide thin films tend to exhibit a porous and pitted structure when deposited by pulsed laser deposition at room temperature under a fairly high oxygen partial pressure (here 0.1 mbar). [ 26 ] The resulting formation of pinholes in the NiO layers hence remarkably enhances the probability of shunt‐induced leakage currents through the gate. Increasing the thickness of the NiO layer by approximately a factor of three to 80 nm yielded an improved and rather constant leakage current for V G < 0 V, as has been reported for ZTO‐based JFETs.…”

The same batch enabled threshold voltage tuning for vertically‐ or laterally‐gated transparent InZnO thin‐film transistors

“…The positive shift of the threshold voltage is similar to a positive shift in the turn‐on voltage ( V on ), where V on is defined to be the gate voltage V GS corresponding to the minimum drain current I DS in the I DS versus V GS transfer characteristic of the TFTs. The calculated V on can be extracted according to the following expression: where is work function difference between channel and gate electrode, e is the electron charge, k the Boltzmann constant, and T the temperature. and is the vacuum permittivity and relative permittivity of the InZnO channel, respectively.…”

“…In general, threshold voltage ( V th ) tuning can provide a convenient way to achieve expected enhancement mode (E‐mode, V th ≥ 0) devices, which is beneficial to reduced power consumption compared to the depletion mode (D‐mode, V th < 0) . As recently stated by M. Lorenz et al , the threshold voltage can be varied by the following three methods: (i) variation of the channel thickness; (ii) variation of the intrinsic electron concentration within the channel; and (iii) work function difference between the channel and the gate electrode. Among them, varying the channel layer thickness is a simple but effective method for tuning threshold voltage in TFTs .…”