2010 12th Biennial Baltic Electronics Conference 2010
DOI: 10.1109/bec.2010.5631145
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Design space exploration and optimisation for NoC-based timing sensitive systems

Abstract: Communication modelling and synthesis plays an important role in the design of complex network-on-chip (NoC) based timing-sensitive systems-on-chip (SoC). To guarantee timing constraints without detailed know-how of communication might lead to unexpected results. In our previous work we have proposed an approach for communication modelling and synthesis to calculate communication hard deadlines that are represented by communication delay and guide the scheduling process to take into account possible network co… Show more

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