Design Space Exploration for Networks On-chip

Villamón, Francisco Gilabert

doi:10.4995/thesis/10251/11521

Cited by 3 publications

(2 citation statements)

References 152 publications

(147 reference statements)

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“…The designer must select the topology, the number of nodes, the size of flits, the commutation mode, the routing algorithm, the size of buffers and many other parameters. Enumerating every point of the design space is prohibitive and is time consuming [28].…”

Section: Motivation Of Workmentioning

confidence: 99%

NoC Dimensioning from Mathematical Models

Fresse¹

2016

IJCDS

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NoCs (Network-on-Chip) have emerged as efficient scalable and low power communication structures for SoC (System-On-Chip). Two main challenges are pointed out when prototyping a SoC on a reconfigurable chip such as FPGA (Field Programmable Gate Array). The first challenge is to tune a NoC according to the application requirements by exploring all design solutions. The second challenge is to dimension the FPGA resources regarding the previously selected appropriate solution. Usually, dimensioning of FPGA resources is done by several runs of automatic synthesis processes to evaluate if the number of resources fits to the selected FPGA device. Finding the most appropriate solution and FPGA dimensioning are time consuming and the design space exploration is not fully done in order to decrease the exploration time. A more appropriate solution would be analytic models of the NoC on a FPGA device. Mathematical modelling consists in identifying links between the NoC parameters and the FPGA resources using a database and in extracting relations between them. In this paper, we present a methodological framework to estimate the number of resources required for a given communication architecture and the task graph of the application. The framework contains 4 steps: the design or the selection of the NoC, the data collection, the data analysis from which a model is deduced. The database obtained in the data collection step contains the synthesized results of each NoC configuration. Two NoCs, with a mesh topology and different characteristics, are used to provide two databases. The methodological framework provides the most appropriate models that are identified using predictive modelling. The evaluation of each model shows that the relative error is less than 5% in most cases. It is therefore possible to tune the most appropriate NoC and to estimate the required resources in a short exploration time without the synthesis steps.

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Section: Motivation Of Workmentioning

confidence: 99%

NoC Dimensioning from Mathematical Models

Fresse¹

2016

IJCDS

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“…The main advantage of a NoC over a shared bus is its capability to reduce design costs while providing highperformance communications. In a NoC, each microcontroller is connected by a Network Interface (NI) to a network link [3]. Those links are point-to-point data lines connected with other links via switches.…”

Section: Design (Noc) Model Of Multi-microcontroller Systemmentioning

confidence: 99%

An Efficient Design of Latches for Multi-Clock Multi-Microcontroller System on Chip for Bus Synchronization

Vishwakarma¹

2015

IJRET

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Speed is a very interesting feature of present time systems either it is electronic or mechanical. From a long time system designers are trying to speed up the system. There are many constraints for the designers as only speed of the system is not required cost, power, size and complexity should not increase up to a certain limit. Now in case of microprocessor/microcontroller speed is the main consideration. No one wants the lower speed microprocessor/microcontroller. Any embedded system speed is dependent on the speed of the processor. Early time processor designers were followed a concept of increasing the number of data lines. In the processor design first four bit microprocessor was developed after that eight, sixteen, thirty two and so on. But soon this concept was saturated as the number of lines increases up to a large extent. The complexity and power dissipation increases due to the increase in the capacitance by these lines. In the same way the concept of pipelining was also saturated after a certain design complexity level. So designers move to a new architecture that is the multi-core architecture. In multi core architecture similar microcontrollers are connected in parallel. These microcontrollers are connected to a common shared bus. So the speed of the multi-microcontroller architecture depends on speed of the interconnection network. This interconnection network is nothing but network-on-chip (NoC). So there is a need of synchronization of the buses of microcontrollers to common shared bus by means of arbitration technique. To synchronize the buses we need tri state buffers/latches. In this paper, we have explored several critical aspects in the design of the latches. Latches are required for the bus synchronization of multi-microcontroller system on programmable chip (MMSoPC).

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