Design Space Pruning Through Early Estimations of Area/Delay Tradeoffs for FPGA Implementations

Abstract

Early performance feedback and design space exploration of complete FPGA designs are still time consuming tasks. We propose an original methodology based on estimations to reduce the impact on design time. We promote a hierarchical exploration to mitigate the complexity of the exploration process. Therefore this work takes place before any design step, such as compilation or behavioral synthesis, where the specification is still provided as a C program. The goal is to provide early area and delay evaluations of many RTL implementations to prune the design space. Two main steps compose the flow: (1) a structural exploration step defines several RTL implementations, and (2) a physical mapping estimation step computes the mapping characteristics of these onto a given FPGA device. For the structural exploration, a simple yet realistic RTL model reduces the complexity and permits a fast definition of solutions. At this stage, we focus on the computation parallelism and memory bandwidth. Advanced optimizations using for instance loop tiling, scalar replacement or data layout are not considered. For the physical estimations, an analytical approach is used to provide fast and accurate area / delay trade-offs. We do not consider the impact of routing on critical paths or other optimizations. The reduction of the complexity allows the evaluation of key design alternatives, namely target device and parallelism that can also include the effect of resource allocation, bitwidth or clock period. Due to this, a designer can quickly identify a reliable subset of solutions for which further refinement can be applied to enhance the relevance of the final architecture and reach a better use of FPGA resources, i.e. an optimal level of performance. Experiments performed with Xilinx (VirtexE) and Altera (Apex20K) FPGAs for a 2D Discrete Wavelet Transform and a G722 speech coder lead to an average error of 10% for temporal values and 18% for area estimations.

Methodology to derive resource aware context adaptable architectures for FPGAs

“…Bilavarn et al [17] propose an algorithm to generate FPGA based architectures for CDFGs using area and delay estimations. They perform design space exploration for a specific RTL architecture template (bus-based architecture), by defining a parameterized architecture, rather than building one.…”

“…After all the DFGs are processed, area estimation for each type of FPGA resource is computed separately for each solution. Unlike [17], in our proposed methodology we perform area estimation during architecture exploration offering instant feedback to the scheduling algorithm, which might yield better results.…”

Design space exploration of multiple loops on FPGAs using high level synthesis

“…Existing works [3] [5][17] [20] that target a single nested loop or multiple loops often ignore interactions and data dependencies among the loops. In this paper, we consider the dataflow dependencies among the loops as our experimental evaluation reveals that such interactions among multiple loops can not be neglected.…”

Multilevel Granularity Parallelism Synthesis on FPGAs

“…Various resource/frequency estimation models have been proposed [16][17][18], but not in conjunction with multigranularity parallelism extraction. In this work, we propose resource and clock period estimation models that predict the resource and clock period as a function of the degrees of different parallelism granularities (array, thread, core and core-cluster).…”