This paper attempts to describe a pipeline architecture synthesis tool dedicated to signal processing applications. This approach relies on the use of a design strategy and of a generic architectural model, using optimized control of resources. GAUTi takes a VHDL description of an application as input, and generates the optimal structural and functional VHDL description of a dedicated architecture. The results obtained by GAUT are intended for an application in acoustic echo cancellation

Early performance feedback and design space exploration of complete FPGA designs are still time consuming tasks. We propose an original methodology based on estimations to reduce the impact on design time. We promote a hierarchical exploration to mitigate the complexity of the exploration process. Therefore this work takes place before any design step, such as compilation or behavioral synthesis, where the specification is still provided as a C program. The goal is to provide early area and delay evaluations of many RTL implementations to prune the design space. Two main steps compose the flow: (1) a structural exploration step defines several RTL implementations, and (2) a physical mapping estimation step computes the mapping characteristics of these onto a given FPGA device. For the structural exploration, a simple yet realistic RTL model reduces the complexity and permits a fast definition of solutions. At this stage, we focus on the computation parallelism and memory bandwidth. Advanced optimizations using for instance loop tiling, scalar replacement or data layout are not considered. For the physical estimations, an analytical approach is used to provide fast and accurate area / delay trade-offs. We do not consider the impact of routing on critical paths or other optimizations. The reduction of the complexity allows the evaluation of key design alternatives, namely target device and parallelism that can also include the effect of resource allocation, bitwidth or clock period. Due to this, a designer can quickly identify a reliable subset of solutions for which further refinement can be applied to enhance the relevance of the final architecture and reach a better use of FPGA resources, i.e. an optimal level of performance. Experiments performed with Xilinx (VirtexE) and Altera (Apex20K) FPGAs for a 2D Discrete Wavelet Transform and a G722 speech coder lead to an average error of 10% for temporal values and 18% for area estimations.

AbsIracf-In this p a p r we resent the intra-function dynamic estimation step of our system-Evel design space exploration tool. The aim of our global methodolow is to fill the eaD between system specilcatl'on and lhe task-of lhe system-d&gn flow to mnverge towards an efhcient System on Chip architecture for multimedia applications. In this contexl the intra-function estimation SteD raoidlv Dmvides. for each hnctional blmk of the specificatiin, liad&otr euw& which re resent a large set of parallelism o tions for both data-transfer and processing resources. A set ofmethods used to achieve this estimation process is detailed.

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Nowadays, interaction with our surrouding environment has increased due to the presence of numerous devices that provide us with services. This is especially true in Smart Homes and can be of great help for the disabled people and the elderly that can no longer perform daily tasks they used to. However, in case of failure, corrective actions can be heavy to take, thus the need for the system to recover by itself and ensure service availability. Service availability is provided through service reconfiguration. This papers deals with service reconfiguration in smart homes. It presents a multi-level approach in which both off-line and on-line reconfiguration schemes are used to gradually recover from failed services. Static, effect-based, path and resource reconfiguration levels are described. They have been successfully implemented in the DANAH assistive system, which combines both navigation and service provision for smart homes.