Design Structures Using Cell Interaction Based XOR in Quantum Dot Cellular Automata

Pittala, Chandra Shaker; Vijay, Vallabhuni; Rani, A. Usha; Kameshwari, R.; Manjula, A.; Haritha, D.; Vallabhuni, Rajeev Ratna

doi:10.1109/icrtcst54752.2022.9781911

Cited by 10 publications

(12 citation statements)

References 7 publications

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“…Due to their higher threshold voltage, previously known methods cannot be operated at low voltages. [32][33][34][35][36][37][38][39] This tells us that the previously known and current known methodologies had a significant drawback which creates the need to invent new methodologies to make the circuit more efficient. It is also known that the static leakage current is also more in existing and previously known methodologies.…”

Section: Significant Drawbacks In the Existed Methodsmentioning

confidence: 99%

ADC: Novel Methodology for Code Converter Application for Data Processing

2023

VLSI

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An innovative "Multiplexer based Thermometer to Binary code encoder" is presented in this paper. This paper shows a relative decrease in the total count of multiplexers used which eventually reduces the no of transistors used when compared to traditional Architectures. The requirement for further more inverters is also eliminated in the proposed model. The input thermometer code is at first is converted to the respective gray code with the help of 2:1 multiplexer. Thereafter, using two-input XOR gates the conversion process of gray code to respective binary codes takes place. Outcomes of simulation reveal that there is an approximately 80% decrease in the power consumption which is a great reduction actually when differentiated with previously known and current encoder architectures with the delay being reduced from 0.472ps to 0.366 ps. This throws a light on modern power-saving encoder architectures and has a greater significance in the future. The proposed encoder gives a better application for future generation advanced ADC & related circuits.

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Section: Significant Drawbacks In the Existed Methodsmentioning

confidence: 99%

ADC: Novel Methodology for Code Converter Application for Data Processing

2023

VLSI

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“…It can also be performed with help of carry look-ahead logic in which the relation between operands is defined by generate bits and propagate bits. [5] The existing designs include serial and parallel structured comparators. [6] The disadvantage with these comparators is that they provide less efficiency with respective to large inputs.…”

Section: Existing Comparatorsmentioning

confidence: 99%

Data Distinguisher Module Implementation using CMOS Techniques

2023

VLSI

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Comparator plays a vital role in many IC applications, Microprocessors, computer systems etc. Hence it is desirable to design a comparator block with low power consumption and high speed performance .In this paper a novel architecture of 32-bit comparator using Complementary metal-oxide semiconductor logic is proposed and computed its delay and power metrics. Further it is compared with the full adder based 32-bit comparator. From the analysis we derive the comparison between proposed and the conventional comparator. The complete designing of architectures and their result analysis was done in cadence virtuoso tool at 180 nm technology. Simulation results show that there is reduce in power consumption of 90% when compared to the conventional full adder based comparator.

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“…These effects are studied and discussed in. [3] The optimizations in the FinFET devices are discussed in [4] for low power and delay. FinFET circuits are designed at low power, and they are analyzed at multiple threshold voltages and supply voltages in.…”

Section: Introductionmentioning

confidence: 99%

Fundamental Flip-Flop Design: Comparative Analysis

2023

VLSI

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A latch is used to store single bit information. It is a level triggered device. These are the building blocks for sequential circuits. The basic working of D-Latch is that input data will be transferred to the output node whenever the clock or enable signal is high. In this paper, various efficient designs of d-latch using 18nm FinFET technology are proposed. The designing of latches are very flexible when compared with flip flops. FinFET technology has many advantages over planar CMOS, such as lower leakage current and lower power consumption. The circuits are designed and simulated using FinFET spectre models in cadence virtuoso tool. The proposed latches using FinFET consumes less power and has low power delay product when compared to traditional D-Latch designs.

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Design Structures Using Cell Interaction Based XOR in Quantum Dot Cellular Automata

Cited by 10 publications

References 7 publications

ADC: Novel Methodology for Code Converter Application for Data Processing

ADC: Novel Methodology for Code Converter Application for Data Processing

Data Distinguisher Module Implementation using CMOS Techniques

Fundamental Flip-Flop Design: Comparative Analysis

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