Design Techniques for Ultra-Low Voltage Analog Circuits Using CMOS Characteristic Curves: a practical tutorial

Girardi, Alessandro; Severo, Lucas Compassi; Aguirre, Paulo César C. de

doi:10.29292/jics.v17i1.573

Cited by 8 publications

(7 citation statements)

References 0 publications

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“…Consequently, the moderated channel inversion level (MI) is the most favorable region of the CMOS transistors operation for the modern low-power RF circuits. The current density at MI is lower than the SI but an improved g m /I D ratio can be obtained [15]. In comparison to the weak inversion, the operation at MI results in reduced parasitic capacitance due to the relatively lower transistor sizes.…”

Section: Low Voltage Biasing Analysismentioning

confidence: 96%

0.4 V Active Biased LNA for 2.4 GHz Low Energy RF Receivers

Ceolin¹,

Severo²

2022

JICS

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To meet low power requirements for Internet of Things (IoT) applications, the power dissipation of RF transceivers must be very low. As the Low Noise Amplifier (LNA) is one of the most energy consuming parts of an RF receiver, its power optimization is necessary for modern IoT devices. This work presents a 170 $\mu$W LNA capable of operating at 2.4 GHz when powered by a 0.4 V source. It is based on an inverter-based amplifier with improved gate bias voltage and automatic forward bulk biasing to operate at the moderated channel inversion level. A biasing metric is explored to analyze the best dimensions and bulk bias voltages for the NMOS transistor. Post-layout simulation results shown a 2.8 dB noise and competitive specification values compared to the state-of-the-art low-voltage LNAs.

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Section: Low Voltage Biasing Analysismentioning

confidence: 96%

0.4 V Active Biased LNA for 2.4 GHz Low Energy RF Receivers

Ceolin¹,

Severo²

2022

JICS

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“…According to [75], [76], a MOS transistor operates in the deep subthreshold region when its inversion coefficient IC is lower than 0.01. A value of IC of 0.01 corresponds to an overdrive voltage V OV = (V gs −V T H ) equal to -145mV (V gs and V T H denote the gate-source voltage and the threshold voltage of the MOS device, respectively).…”

Section: Conditions For Triode and Saturation Operation Of Mos Device...mentioning

confidence: 99%

On the Feasibility of Cascode and Regulated Cascode Amplifier Stages in ULV Circuits Exploiting MOS Transistors in Deep Subthreshold Operation

Della Sala,

Centurelli,

Monsurró

et al. 2024

IEEE Access

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In the last years several ultra-low voltage (ULV) operational transconductance amplifiers (OTAs) with supply voltages below 0.5V have been proposed in the literature. To achieve high gain, multistage amplifiers are frequently exploited, in spite of the complexity of design and compensation approaches, whereas cascode and regulated-cascode OTA topologies have rarely been exploited to implement ULV amplifiers. On the other hand, most ULV amplifiers are designed for IoT and biomedical applications in which reducing power consumption is the most important specification, and MOS devices are operated in the subthreshold region. This paper focuses on exploiting the subthreshold operating region to design ULV single-stage OTAs that utilize an output cascoded branch to increase the equivalent output resistance and, consequently, the overall voltage gain. A detailed analytical study of the conditions for triode and saturation regions for MOS devices operating in deep subthreshold region is presented to demonstrate that, for an appropriate choice of the inversion coefficient (IC), a cascode configuration exhibits higher gain than a single transistor, for the same voltage overhead, even in ULV conditions. More specifically, the results presented in this work demonstrate that 4 MOS devices (2 NMOS and 2 PMOS) can be reliably stacked to build a complementary cascode amplifier, even with a supply voltage as low as 0.4V. We also present a novel topology of regulated-cascode amplifier suitable to be operated with a supply voltage of 0.4V and a voltage gain approaching 100dB. Simulation results referring to a 180nm CMOS technology and including PVT and mismatch variations confirm state-of-the-art performances, as well as the good robustness of the proposed regulated-cascode ULV OTA.

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“…Figure 16 presents the proposed OTA topology used in this work. The first stage topology is an improved version of the topology originally presented in [26] and its modifications [27]. The main inverters are composed of transistors Ma1 − Ma2 and Ma11 − Ma12.…”

Section: A First Otamentioning

confidence: 99%

Behavioral and Electrical Modeling of a 0.5-V Third-Order Continuous-Time Sigma-Delta Modulator with FIR DAC for Audio Applications

Cortez

Girardi

Severo

et al. 2023

JICS

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Most mobile and wearable devices present digital audio signal processing capabilities. Since the nature of audio signals is analog, there is a need to use analog-to-digital converters (ADCs) with high-resolution for a high signal-to-noise ratio audio acquisition. This paper presents the high-level modeling and design of a continuous-time third-order sigma-delta modulator (CT-SDM) with an FIR DAC for audio devices, using a supply voltage of 0.5 V. The design is divided in three steps and is carried out using the Delta-sigma toolbox and a discrete-time to continuous-time (DT-CT) transformation. First, the schematic implementation with verilogA models is done to estimate the first-integrator amplifier specifications for the modulator to provide 14 bits of ENOB. Following, a two-stage inverter-based amplifier is designed and used to verify the design strategy. Finally, a transistor-level implementation of OTAs and comparator is done to evaluate the CT-SDM performance. An in-depth analysis and discussion are presented to explain the achieved results with those transistor-level circuits.

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Design Techniques for Ultra-Low Voltage Analog Circuits Using CMOS Characteristic Curves: a practical tutorial

Cited by 8 publications

References 0 publications

0.4 V Active Biased LNA for 2.4 GHz Low Energy RF Receivers

0.4 V Active Biased LNA for 2.4 GHz Low Energy RF Receivers

On the Feasibility of Cascode and Regulated Cascode Amplifier Stages in ULV Circuits Exploiting MOS Transistors in Deep Subthreshold Operation

Behavioral and Electrical Modeling of a 0.5-V Third-Order Continuous-Time Sigma-Delta Modulator with FIR DAC for Audio Applications

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