Design Technology Co-Optimization for Cold CMOS Benefits in Advanced Technologies

Chiang, Hung-Li; Wu, J. J.; Chou, Chen-Han; Hsiao, Yen-Fu; Chen, Yi‐Chun; Liu, Chengxi; Wang, Jer-Fu; Chen, Tzu-Chiang; Liao, Pei-Jun; Cai, Jin; Bao, Xinyu; Cheng, Alan; Chang, Meng‐Fan

doi:10.1109/iedm19574.2021.9720573

Cited by 7 publications

(4 citation statements)

References 5 publications

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“…在集成电路设计领域内, 若干个反相器首尾相接组成的环形振荡器 (环振) 经常被用于评估数字电路的性能. 2021 年台积电对 5 nm FinFET 工艺的 101 级环振进行分析, 相同振荡频率下 77 K 的功耗降低到室温的 40%, 而相同功耗下 77 K 的速度提升到室温的 1.4 倍 [23] , 说明低温下经典电路实现高性能计算的可行性. 经典计算机结构包含存储部分、计算部分、输入输出以及控制部分, 其中的存储部分和计算部分在低温下均有着不同程度的性能提升.…”

Section: 低温逻辑电路的应用探索unclassified

“…2018 年 Rambus 公司的研究人员在 360∼77 K 温度范围内对商用 DRAM 进行测试, 发现当温度降低时 DRAM 的保留时间大幅增加, 77 K 温度下甚至超过了 90 min [24] . 2021 年台积电对 5 nm FinFET 在 298∼77 K 的宽温度范围下建模, 并对 6T-SRAM 进行分析, 发现 77 K 下其速度是室温下的 1.4 倍, 若再使用设计制造协同优化技术 (design technology co-optimization, DTCO) 针对低温 CMOS 的能效进行优化, 可使 SRAM 在相同功率下实现 1.7 倍的速度增益, 或者在相同速度下仅需 20% 的功耗 [23] . 在 SRAM 单元和外围电路中有 50% 的速度增益来源于 DTCO, 这也体现协同定制器件的设计对于低温逻辑电路的关键性.…”

Section: 低温逻辑电路的应用探索unclassified

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Low-temperature CMOS technology for high-performance computing: development and challenges

CHENG,

LI,

WANG

et al. 2024

Sci. Sin.-Inf.

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等)、非超导存储器 (包括易失的静态随机存储器 (static random access memory, SRAM) [7] 、动态随机存储器 (dynamic random access memory, DRAM) [8] 、非易失的阻变存储器 (resistive random access memory, RRAM) [9] 、铁电存储器 (ferroelectric random access memory, FeRAM)、磁存储器 (magnetic random access memory, MRAM)、相变存储器 (phase-change random access memory, PCRAM) 等) 以

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Section: 低温逻辑电路的应用探索unclassified

Low-temperature CMOS technology for high-performance computing: development and challenges

CHENG,

LI,

WANG

et al. 2024

Sci. Sin.-Inf.

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“…Recently, a cryo-CMOS is re-cool since operating it at liquid-nitrogen temperatures improves the performance of high-performance computing (HPC). Therefore, the cryo-CMOS technology is extensively studied [8], [9]. To design the CMOS circuits at cryogenic temperature, the cryogenic MOS transistor model [10] and the cell library have been reported [11].…”

Section: Introductionmentioning

confidence: 99%

A 65nm Cryogenic CMOS Design and Performance at 4.2K for Quantum State Controller Application

Tada,

Okamoto,

Tanaka

et al. 2024

IEEE J. Electron Devices Soc.

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A performance evaluation of cryogenic CMOS circuit at liquid-helium temperature (4.2K) is conducted using a standard 65nm bulk CMOS for quantum state controller (QSC) applications. The ON-current (Ion) of the core n/pMOSFET are increased by 25% and 9% with excellent gate modulation (Ion/Ioff=~10 9 ). The cryogenic characteristics of copper interconnects in the back end of the line (BEOL), including line and via resistances, capacitances, and Joule-heating effect (JHE) are accurately assessed. The interconnect and via resistances decrease with temperature due to a reduction of electron-phonon scattering, resulting in resistances that are 75% and 20% lower at 4.2K compared to those at room temperature (RT). No significant change in inter-line capacitance and no severe JHE are observed in the Cu BEOL at 4K. The developed cell libraries for Simulation Program with Integrated Circuit Emphasis (SPICE) model and the technology file, which includes RC interconnect parameters, enable precise design of CMOS circuits at 4.2K. This results in a demonstrated +18.3% increase in speed or -16% reduction in power consumption for ring-oscillator (ROSC) at 4.2K, aligning well with the simulation results obtained from the developed model.

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“…Example studies include Lee et al's proposed CryoGuard, a robust, near refresh-free DRAM operating at 77 K [8]; Byun et al's 77 K processor architecture, which demonstrated 3.4 times performance improvement [11]. Similarly, TSMC achieved an impressive 70% reduction in SRAM read latency using a 5 nm FinFET process at 77 K [12]. These research efforts not only underscore the significance of temperature management in advancing HPCs, but also highlight the requirements for deep understanding of cryogenic device physics.…”

Section: Introductionmentioning

confidence: 99%

Nonlinear behaviors in back-gate effects of FDSOI MOSFETs at cryogenic temperatures

Hu,

Ren,

Yin

et al. 2024

Semicond. Sci. Technol.

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In this work, we systematically investigate the DC performance of Fully Depleted Silicon-on-insulator (FD-SOI) MOSFETs at both room and cryogenic temperatures as low as 77 K. The influences of back-gate bias on normal and flip-well devices are measured and analyzed. Both types devices display non-linear behaviors when adjusting the back-gate voltage at cryogenic temperatures. Notably, the non-linear effects are more prominent in normal-well devices. The possible reasons are analyzed and verified by TCAD simulation, suggesting that normal-well devices are more susceptible to the formation of depletion regions between the buried oxide layer and the well. This phenomenon disrupts the linearity of the back-gate effect. This research contributes to understanding and characterizing of the back-gate effects in cryogenic environments and holds potential for high-performance computing applications.

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Design Technology Co-Optimization for Cold CMOS Benefits in Advanced Technologies

Cited by 7 publications

References 5 publications

Low-temperature CMOS technology for high-performance computing: development and challenges

Low-temperature CMOS technology for high-performance computing: development and challenges

A 65nm Cryogenic CMOS Design and Performance at 4.2K for Quantum State Controller Application

Nonlinear behaviors in back-gate effects of FDSOI MOSFETs at cryogenic temperatures

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