Design-technology co-optimization for OxRRAM-based synaptic processing unit

Mallik, Arindam; Garbin, Daniele; Fantini, A.; Rodopoulos, Dimitrios; Degraeve, R.; Stuijt, Jan; Das, Anup; Schaafsma, Siebren; Debacker, Peter; Donadio, Gabriele Luca; Hody, Hubert; Goux, L.; Kar, Gouri Sankar; Furnemont, A.; Mocuta, A.; Raghavan, P.

doi:10.23919/vlsit.2017.7998166

Cited by 54 publications

(47 citation statements)

References 3 publications

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“…Burr et al propose to use phase-change memories (PCM) to design neuromorphic crossbars [22]. Mallik et al propose to use oxidebased resistive RAM (OxRAM) as alternative [54]. While all these orthogonal works focus on the design of a crossbar, we focus on the architecture of a neuromorphic chip integrating multiple such crossbars.…”

Section: B Neuromorphic Hardwarementioning

confidence: 99%

Mapping Spiking Neural Networks to Neuromorphic Hardware

Balaji

Catthoor

Das

et al. 2020

IEEE Trans. VLSI Syst.

124

144

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Neuromorphic hardware platforms implement biological neurons and synapses to execute spiking neural networks (SNNs) in an energy-efficient manner. We present SpiNeMap, a design methodology to map SNNs to crossbar-based neuromorphic hardware, minimizing spike latency and energy consumption. SpiNeMap operates in two steps: SpiNeCluster and SpiNePlacer. SpiNeCluster is a heuristic-based clustering technique to partition SNNs into clusters of synapses, where intracluster local synapses are mapped within crossbars of the hardware and inter-cluster global synapses are mapped to the shared interconnect. SpiNeCluster minimizes the number of spikes on global synapses, which reduces spike congestion on the shared interconnect, improving application performance. SpiNePlacer then finds the best placement of local and global synapses on the hardware using a meta-heuristic-based approach to minimize energy consumption and spike latency. We evaluate SpiNeMap using synthetic and realistic SNNs on the DynapSE neuromorphic hardware. We show that SpiNeMap reduces average energy consumption by 45% and average spike latency by 21%, compared to state-of-the-art techniques.

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Section: B Neuromorphic Hardwarementioning

confidence: 99%

Mapping Spiking Neural Networks to Neuromorphic Hardware

Balaji

Catthoor

Das

et al. 2020

IEEE Trans. VLSI Syst.

124

144

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“…The resistance switching random access memory (OxR-RAM) technology presents an attractive option for implementing the synaptic cells of a crossbar due to its demonstrated potential for low-power multilevel operation and high integration density [2]. An OxRRAM cell is composed of an insulating film sandwiched between conducting electrodes forming a metal-insulator-metal (MIM) structure (see Figure 2).…”

Section: A Oxide-based Resistive Ram (Oxrram) Technologymentioning

confidence: 99%

“…Here, neural circuity is tightly coupled with synaptic storage, which eliminates the performance and energy bottlenecks of sharedmemory systems for machine learning inference [1]. Non-Volatile Memory (NVM) cells such as oxide-based resistive switching random access memory (OxRRAM) can implement multilevel analog operations, which make them ideal candidates for storing model parameters, i.e., the synaptic weights of a machine learning model [2].…”

Section: Introductionmentioning

confidence: 99%

On the Mitigation of Read Disturbances in Neuromorphic Inference Hardware

Paul¹,

Song²,

Titirsha³

et al. 2022

Preprint

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Non-Volatile Memory (NVM) cells are used in neuromorphic hardware to store model parameters, which are programmed as resistance states. NVMs suffer from the read disturb issue, where the programmed resistance state drifts upon repeated access of a cell during inference. We show that resistance drifts can lower the inference accuracy. To address this, it is necessary to periodically reprogram model parameters to the hardware (a high overhead operation). We study read disturb failures of an NVM cell. Our analysis show both a strong dependency on model characteristics such as synaptic activation and criticality, and on the voltage used to read resistance states during inference. We propose a system software framework to incorporate such dependencies in programming model parameters on NVM cells of a neuromorphic hardware. At the core of our framework is a convex optimization formulation which aims to implement synaptic weights that have more activations and are critical, i.e., those that have high impact on accuracy on NVM cells that are exposed to lower voltages during inference. In this way, we increase the time interval between two consecutive reprogramming of model parameters. We evaluate our system software with many emerging inference models on a neuromorphic hardware simulator and show a significant reduction in the system overhead.

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“…pre-synaptic neurons while the vertical wires are connected to post-synaptic neurons. Non-Volatile Memory (NVM) cells are placed at the crosspoints of each crossbar to implement storage of synaptic weights [24,72]. 1 [25], which is representative of many neuromorphic platforms such as DYNAP-SE [73], TrueNorth [47], and Loihi [45].…”

Section: Introductionmentioning

confidence: 99%

DFSynthesizer: Dataflow-based Synthesis of Spiking Neural Networks to Neuromorphic Hardware

Song

Chong

Balaji

et al. 2022

ACM Trans. Embed. Comput. Syst.

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Spiking Neural Networks (SNN) are an emerging computation model, which uses event-driven activation and bio-inspired learning algorithms. SNN-based machine-learning programs are typically executed on tile-based neuromorphic hardware platforms, where each tile consists of a computation unit called crossbar, which maps neurons and synapses of the program. However, synthesizing such programs on an off-the-shelf neuromorphic hardware is challenging. This is because of the inherent resource and latency limitations of the hardware, which impact both model performance, e.g., accuracy, and hardware performance, e.g., throughput. We propose DFSynthesizer, an end-to-end framework for synthesizing SNN-based machine learning programs to neuromorphic hardware. The proposed framework works in four steps. First, it analyzes a machine-learning program and generates SNN workload using representative data. Second, it partitions the SNN workload and generates clusters that fit on crossbars of the target neuromorphic hardware. Third, it exploits the rich semantics of Synchronous Dataflow Graph (SDFG) to represent a clustered SNN program, allowing for performance analysis in terms of key hardware constraints such as number of crossbars, dimension of each crossbar, buffer space on tiles, and tile communication bandwidth. Finally, it uses a novel scheduling algorithm to execute clusters on crossbars of the hardware, guaranteeing hardware performance. We evaluate DFSynthesizer with 10 commonly used machine-learning programs. Our results demonstrate that DFSynthesizer provides much tighter performance guarantee compared to current mapping approaches.

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Design-technology co-optimization for OxRRAM-based synaptic processing unit

Cited by 54 publications

References 3 publications

Mapping Spiking Neural Networks to Neuromorphic Hardware

Mapping Spiking Neural Networks to Neuromorphic Hardware

On the Mitigation of Read Disturbances in Neuromorphic Inference Hardware

DFSynthesizer: Dataflow-based Synthesis of Spiking Neural Networks to Neuromorphic Hardware

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