Design Through Verilog HDL

Padmanabhan, T. R.; Sundari, B. Bala Tripura

doi:10.1002/0471723002

Cited by 14 publications

(9 citation statements)

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“…Simulation or changes in the design description together form a cyclic iterative process and repeated untill an error free design is evolved. [5] ASIC's are broadly classified into three types they are:…”

Section: Asic Design Flow Application Specific Integrated Circuitmentioning

confidence: 99%

SURVEY: DESIGN PROCEDURE OF VLSI, FPGA & ASIC LIFE CYCLES

2017

IJAERD

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Section: Asic Design Flow Application Specific Integrated Circuitmentioning

confidence: 99%

SURVEY: DESIGN PROCEDURE OF VLSI, FPGA & ASIC LIFE CYCLES

2017

IJAERD

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“…Both the lectures and the practical work follow the design methodology for top-down SoC design [4], [5]. This methodology partitions the design into a number of stages where one level is designed, tested, and modified until correct.…”

Section: System-on-chip Design Hierarchymentioning

confidence: 99%

“…Thus, the next stage in the design process is to specify the internal hardware of each module, as a behavioral model, using a hardware description language that can be synthesized by software tools to provide a logic implementation. The Verilog hardware description language [5], [16], [17] is chosen since this is the most commonly used in industry, and hence, the software CAD tools are designed to work with this language, including the processing tools mapping a logic design onto a hardware implementation. The Verilog simulation of the RTL design runs under the Cadence CAD environment.…”

Section: Rtl Designmentioning

confidence: 99%

System-on-Chip Design and Implementation

2010

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Abstract-The system-on-chip module described here builds on a grounding in digital hardware and system architecture. It is thus appropriate for third-year undergraduate computer science and computer engineering students, for post-graduate students, and as a training opportunity for post-graduate research students. The course incorporates significant practical work to illustrate the material taught and is centered around a single design example of a drawing machine. The exercises are composed so that students can regard themselves as part of a design team where they undertake the complete design of their own particular section of the system. These design tasks range from algorithmic specification and transaction-level modeling (TLM) of the architecture down to describing the design at the register transfer level (RTL) with subsequent verification of their prototype on a field-programmable gate array (FPGA). With this approach, students are able to explore and gain experience of the different techniques used at each level of the design hierarchy and the problems in translating to the next level down. Throughout the module, there is emphasis on using industry standard tools for the modeling and simulation, leading to the use of the SystemC and Verilog hardware description languages and Cadence for the simulation environment.Index Terms-Integrated circuit design, large-scale systems modeling, system-level design, system-on-chip, systems engineering education, transaction-level modeling (TLM).

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“…The compiler is eventually called upon to synthesize whole module to generate a complex circuit. Verilog HDL helps hardware designers to describe a complex digital circuit within a wide range of levels of abstraction, based on either top-down or bottom-up synthesis approaches [5]. To simulate a digital circuit in Verilog HDL, a testbench is written, which includes an instantiation of digital circuit.…”

Section: Design Details Of Hardware Environmentmentioning

confidence: 99%

Further studies on improved test efficiency in cores-based system-on-chips using ModelSim verification tool

Das

Hossain

et al. 2009

2009 IEEE Intrumentation and Measurement Technology Conference

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The complexity of modern digital circuits has increased enormously because of paradigm shift from system-onboard to designs embracing embedded cores-based system-onchips (SOCs). The ensuing intricacy has resulted in a huge challenge in setting up their appropriate fault analysis and testing environment. Though enormous efforts were directed to rapidly test very large-scale integration (VLSI) circuit chips under reasonable cost constraints, with technological advances, new barriers emerged. The subject paper, augmenting earlier works of authors, pertains to developing method that aims to test verify circuit architecture in a hardware-software co-design environment, specifically targeting embedded SOCs. The concept of design-for-testability (DFT) is utilized in this paper, using ModelSim simulation and verification tool, to test simulate the overall design. In earlier works, simulation experience on ISCAS 85 combinational benchmark circuits was provided. In this study, some partial simulation results on ISCAS 89 full scan sequential benchmark circuits are furnished because of space contraint, along with discussion of proposed algorithm and programming basisin a context of ModelSim.

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Design Through Verilog HDL

Cited by 14 publications

References 0 publications

SURVEY: DESIGN PROCEDURE OF VLSI, FPGA & ASIC LIFE CYCLES

SURVEY: DESIGN PROCEDURE OF VLSI, FPGA & ASIC LIFE CYCLES

System-on-Chip Design and Implementation

Further studies on improved test efficiency in cores-based system-on-chips using ModelSim verification tool

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