Design verification and functional testing of finite state machines

Abstract

The design of a finite state machine can be verified by simulating all its state transitions. Typically, state transitions involve many don't care inputs that must be fully expanded for an exhaustive functional ver%fication. However, b y exploiting the knowledge about the design structure it is shown that only a f e w vectors from the fully expanded set sufice f o r both design verification and testing for manufacturing defects. The main contributions of the paper include a unified fault model for design errors and manujacturing faults and a functionbased analysis of the circuit structure for the purpose of generating tests under the unified model. Experimental results on benchmark finite state machines are presented in support of this approach to test generation.

Finite State Machines With Input Multiplexing: A Performance Study

“…This approach includes optimization techniques and an architecture, hereinafter called FSMIM with transition-based input selection (FSMIM-T), which uses a multiplexer bank as address modifier. In [6], significant speed improvements and area reductions have been obtained by FSMIM implementations on FPGAs due to the following two facts: 1) typically, a state transition involves many don't care inputs [9] and 2) current FPGAs allow very efficient implementations of wide multiplexers by using dedicated multiplexers [10].…”