Design-Window Methodology for Inductorless Noise-Cancelling CMOS LNAs

Abstract

This paper presents an optimization methodology for inductorless noise-cancelling CMOS Low-Noise Amplifiers (LNA), whose performance typically depends on a tight balance in the design of two transistor stages. Due to the different functions of the two parts, noise-cancelling amplifiers become very difficult to analyze in detail by closed-form expressions or straight simulations: each section significantly affects the results of the other. In addition, opposed specifications, such as gain and cut-off frequency, suppose another grade of complexity due to the interplay of the two branches of the circuit. As a solution, the proposed methodology uses a visualization of the design window in 2-dimensional space to optimize the different parameters of the specifications without compromising the others. All specification constraints are represented in a single figure instead of one graph per parameter. Compared with most optimization methods, the design window methodology observes the design span instead of isolated design points that might not guarantee feasibility. Furthermore, as a simulation-driven exploration method, it benefits from complete device models with high-order effects that would be too complex to include in analytical expressions but critical to achieving maximum efficiency. As an example of the method, the paper describes the optimization of the well-known CS-CG noisecancelling LNA in 65-nm standard CMOS technology. Final post-layout simulations report very competitive results with a 3.7-dB noise figure, a 17-dB gain, and a cut-off frequency above 7 GHz.

Graphical Design Approach for UWB Stacked CG LNA Using Inversion Coefficient

“…So, basically, the optimization process is conducted graphically by selecting the most appropriate IC that satisfies all the design constraints and maximizes FoM. It is worth noting that unlike the methodologies in [5,6], the adopted approach offers a complete analytical solution where every device parameter as well as the transistor biasing point and sizing can be predicted analytically. Moreover, the design steps do not require lengthy iterations and trials, like in the cases of [10] or [11].…”

“…The main drawback of this approach is that it requires the user to perform a full characterization of the MOSFET under all size and bias conditions to build LUTs for each device parameter. Another LUT-based methodology is found in [6], where the gate-source voltage is chosen to maximize linearity while the transistors' widths are chosen to maximize other LNA specifications. This method also requires full MOSFET characterization prior to the design phase.…”