Designing a hardware in the loop wireless digital channel emulator for software defined radio

Matai, Janarbek; Meng, Pingfan; Wu, Lingjuan; Weals, B.T.; Kastner, Ryan

doi:10.1109/fpt.2012.6412135

Cited by 25 publications

(3 citation statements)

References 13 publications

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“…Restructured code typically differs substantially from a software implementation -even one that is highly optimized. A number of studies suggest that restructuring code is an essential step to generate an efficient FPGA design [46,47,15,14,39]. Thus, in order to get an efficient hardware design, the user must write restructured code with the underlying hardware architecture in mind.…”

Section: Restructured Codementioning

confidence: 99%

Parallel Programming for FPGAs

Kastner¹,

Matai²,

Neuendorffer³

2018

Preprint

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Many people have contributed to making this book happen. Probably first and foremost are the many people who have done research in the area of High-Level Synthesis. Underlying each of the applications in this book are many individual synthesis and mapping technologies which combine to result in high-quality implementations.Many people have worked directly on the Vivado R HLS tool over the years. From the beginning in Jason Cong's research group at UCLA as the AutoPilot tool, to making a commercial product at AutoESL Inc., to widespread adoption at Xilinx, it's taken many hours of engineering to build an effective tool. To Zhiru Zhang, Yiping Fan, Bin Liu, Guoling Han, Kecheng Hao, Peichen Pan, Devadas Varma, Chuck Song, and many others: your efforts are greatly appreciated.The idea for this book originally arose out of a hallway conversation with Salil Raje shortly after Xilinx acquired the AutoESL technology. Much thanks to Salil for his early encouragement and financial support. Ivo Bolsens and Kees Vissers also had the trust that we could make something worth the effort. Thanks to you all for having the patience to wait for good things to emerge. This book would not have been possible without substantial support from the UCSD Wireless Embedded Systems Program. This book grew out of the need to make a hardware design class that could be broadly applicable to students coming from a mix of software and hardware backgrounds. The program provided substantial resources in terms of lab instructors, teaching assistants, and supplies that were invaluable as we developed (and re-developed) the curriculum that eventually morphed into this book. Thanks to all the UCSD 237C students over the years for providing feedback on what made sense, what didn't, and generally acting as guinea pigs over many revisions of the class and this book. Your suggestions and feedback were extremely helpful. A special thanks to the TAs for these classes, notable Alireza Khodamoradi, Pingfan Meng, Dajung Lee, Quentin Gautier, and Armaiti Ardeshiricham; they certainly felt the growing pains a lot more than the instructor.Various colleagues have been subjected to early drafts of the book, including Zhiru Zhang, Mike Wirthlin, Jonathan Corbett. We appreciate your feedback.

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Section: Restructured Codementioning

confidence: 99%

Parallel Programming for FPGAs

Kastner¹,

Matai²,

Neuendorffer³

2018

Preprint

Self Cite

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“…In [17], wireless channel emulation for radio bandwidths up to 100 MHz was presented for mmWave massive MIMO. In [18] the design and implementation of a digital wireless channel emulator for a 30 MHz baseband Software Defined Radio (SDR) was presented. In [19], a channel emulator with 2 MHz bandwidth based on a non‐WSSUS (Wide Sense Stationary Uncorrelated Scatterers) channel model for vehicular communications using SDR devices was presented.…”

Section: Introductionmentioning

confidence: 99%

Design and implementation of a wideband channel emulation platform for 5G mmWave vehicular communication

2020

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“…The software simulation approach, besides its great advantage in high‐level system modeling, does not provide the capability to verify low‐level hardware and real‐time software implementations of the system components, which tend to be much more complex than their behavioral models used in simulations. To verify whether the product is correct in terms of implementation and meets the requirements, the HIL 6‐10 technique may be used as a trade‐off between software simulation and hardware evaluation. In this approach, the design under test (DUT), that is, an actual device or a module being validated, interacts with software behavioral models simulating the remaining part of the system through standard external interfaces of the tested device or module.…”

Section: Introductionmentioning

confidence: 99%

Validation of cloud‐radio access network control unit with intra‐PHY architecture: Hardware‐in‐the‐loop framework based on frequency‐domain channel models

Cisek

Zieliński

2020

Trans Emerging Tel Tech

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In this article, a signal processing framework for hardware‐in‐the‐loop (HIL) validation of the cloud‐radio access network (C‐RAN) control unit (CU) with a crosshaul intra‐PHY architecture split is evaluated. The framework is based on the assumption that data exchanged over the crosshaul interface between the lower and higher parts of the physical layer have the form of frequency‐domain orthogonal frequency division multiplexing (OFDM) subcarriers. Therefore, it is proposed to simulate the effects of a wireless fading channel directly in the frequency domain, instead of the conventionally selected time domain. This approach leads to complexity reduction of the channel simulation model by minimizing the number of required FFT/IFFT operations, at the cost of simulation accuracy in high‐mobility and high‐delay spread scenarios. Analysis of bit error ratio (BER) and block error ratio (BLER) metrics obtained using both time‐ and frequency‐domain channel models is presented in order to validate the proposal and evaluate the accuracy loss caused by the usage of nonideal frequency‐domain models. The frequency‐domain methods are compared against the conventional wide sense stationary uncorrelated scattering (WSSUS) model implementation based on the tapped delay line (TDL). It is shown that the utilization of improved frequency‐domain models instead of the block‐fading model substantially decreases the BER/BLER prediction error in specific scenarios.

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Designing a hardware in the loop wireless digital channel emulator for software defined radio

Cited by 25 publications

References 13 publications

Parallel Programming for FPGAs

Parallel Programming for FPGAs

Design and implementation of a wideband channel emulation platform for 5G mmWave vehicular communication

Validation of cloud‐radio access network control unit with intra‐PHY architecture: Hardware‐in‐the‐loop framework based on frequency‐domain channel models

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