Designing Application-Specific Networks on Chips with Floorplan Information

Abstract

With increasing communication demands of processor and memory cores in Systems on Chips (SoCs), scalable Networks on Chips (NoCs) are needed to interconnect the cores. For the use of NoCs to be feasible in today's industrial designs, a custom-tailored, application-specific NoC that satisfies the design objectives and constraints of the targeted application domain is required. In this work, we present a design methodology that automates the synthesis of such application-specific NoC architectures. We present a floorplan aware design method that considers the wiring complexity of the NoC during the topology synthesis process. This leads to detecting timing violations on the NoC links early in the design cycle and to have accurate power estimations of the interconnect. We incorporate mechanisms to prevent deadlocks during routing, which is critical for proper operation of NoCs. We integrate the NoC synthesis method with an existing design flow, automating NoC synthesis, generation, simulation and physical design processes. We also present ways to ensure design convergence across the levels. Experiments on several SoC benchmarks are presented, which show that the synthesized topologies provide a large reduction in network power consumption (2.78× on average) and improvement in performance (1.59× on average) over the best mesh and mesh-based custom topologies. An actual layout of a multimedia SoC with the NoC designed using our methodology is presented, which shows that the designed NoC supports the required frequency of operation (close to 900 MHz) without any timing violations. We could design the NoC from input specifications to layout in 4 hours, a process that usually takes several weeks.

Comparing Energy and Latency of Asynchronous and Synchronous NoCs for Embedded SoCs

“…While it is extensible with new algorithms and components, it does not consider asynchronous network components and, as future work, cites the need for integrating traffic burstiness. For the Xpipes library, a heuristic search determines the topology and router configuration [6]. It uses floorplan information, router energy models, and core communication requirements.…”

Supporting vertical links for 3D networks-on-chip: toward an automated design and analysis flow

“…As discussed in Section II, 3D designs are likely to expose a large degree of heterogeneity, especially along the vertical axis. Therefore, we choose to base our integration effort on the ×pipes [26] NoC library, which supports arbitrary connectivity, and on its instantiation toolchain [33]. Thus, we can leverage a semi-automatic design flow, from RTL description to layoutlevel verification.…”

“…As a first step, we leverage SunFloor [33] to instantiate the 2D mesh. There is no need to modify the RTL output of SunFloor in any way.…”

Algorithm for the Choice of Topology in Reconfigurable On-Chip Networks with Real-Time Support

“…However, although mapping and routing problems are addressed in the paper, topology exploration is not. In [12] the authors use a similar shortest path algorithm for routing but in this case the path selection is not based on timing requirements directly, but rather on energy consumption and operating frequency of the links. The experiments presented in [12] are also based on silicon level simulation.…”

“…In [12] the authors use a similar shortest path algorithm for routing but in this case the path selection is not based on timing requirements directly, but rather on energy consumption and operating frequency of the links. The experiments presented in [12] are also based on silicon level simulation. Although we decided not to conduct experiments on silicone level, the results of our real-time performance oriented work could be used for guidance of low-level implementation.…”