2021
DOI: 10.1109/tvlsi.2021.3105958
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Designing Efficient and High-Performance AI Accelerators With Customized STT-MRAM

Abstract: In this paper, we demonstrate the design of efficient and high-performance AI/Deep Learning accelerators with customized STT-MRAM and a reconfigurable core. Based on modeldriven detailed design space exploration, we present the design methodology of an innovative scratchpad-assisted on-chip STT-MRAM based buffer system for high-performance accelerators. Using analytically derived expression of memory occupancy time of AI model weights and activation maps, the volatility of STT-MRAM is adjusted with process and… Show more

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Cited by 16 publications
(2 citation statements)
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“…Sixth, spin-transfer torque magnetoresistive RAM (STT-MRAM) that has the potential to replace DRAM has not shown vulnerable to rowhammer yet. Therefore, the bit-flip-based adversarial attack is not possible for STT-MRAM-based DNN accelerators [49].…”
Section: Bit-flip Attackmentioning
confidence: 99%
“…Sixth, spin-transfer torque magnetoresistive RAM (STT-MRAM) that has the potential to replace DRAM has not shown vulnerable to rowhammer yet. Therefore, the bit-flip-based adversarial attack is not possible for STT-MRAM-based DNN accelerators [49].…”
Section: Bit-flip Attackmentioning
confidence: 99%
“…The logic-in-memory (LIM) architecture is gaining attention owing to its space-saving structure and increased energy efficiency on integrating logic processes and data storage [4]. Most studies on LIM utilize emerging memories, such as resistive random-access memory (ReRAM) [5,6], spin-transfer torque RAM (STT-RAM) [7,8], and ferroelectric field-effect transistors (FEFETs) [9,10]. However, they comprise non-silicon components that are expensive and require additional fabrication procedures.…”
Section: Introductionmentioning
confidence: 99%