Designing mega-ASICs in nanogate technologies

Lackey, David E.; Zuchowski, Paul S.; Koehl, J.

doi:10.1145/775832.776029

Cited by 10 publications

(4 citation statements)

References 25 publications

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“…Leakage Power dissipation in LSI design has been increasing exponentially with device scaling [1]. Power Gating (PG) is a well-known technique for reducing leakage, in which the power of logic gates with low-Vth is switched by high-Vth power switch transistors.…”

Section: Fine-grained Power Gatingmentioning

confidence: 99%

Trade-off analysis of fine-grained power gating methods for functional units in a CPU

Wang

Ohta

Yoshifumi

et al. 2012

2012 IEEE COOL Chips XV

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High-speed power gating (PG) techniques are useful for reducing leakage power of functional units in a CPU core. This paper analyzes trade off of functional units in a MIPS R3000 based processor with three fine-grained PG methods: the cell-based, row-based and ring-based. Compared with the cell-based PG technique, which was used in our previous work -Geyser-1 processor, the row-based and ring-based PG technique achieved much smaller area and less implemental cost with a certain additional delay to wake-up latency. The simulation results with benchmark programs show that all three methods can reduce leakage power by 28~54% at 25C. (

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Section: Fine-grained Power Gatingmentioning

confidence: 99%

Trade-off analysis of fine-grained power gating methods for functional units in a CPU

Wang

Ohta

Yoshifumi

et al. 2012

2012 IEEE COOL Chips XV

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“…Leakage power dissipation in LSI chips has been increasing exponentially with device scaling [7], and its reducing techniques are indispensable especially for embedded usage. Several techniques have been proposed and some of them are applied to FPGAs.…”

Section: Related Work a Leakage Reduction Techniques For Reconfimentioning

confidence: 99%

“…After 90nm CMOS process, the amount of leakage power is remarkably increased, and it will occupy considerable portion of the total power in the future [7]. Since the leakage power is relational to the chip area, the technique to reduce it will be important especially in DRPAs using a number of PEs.…”

Section: Introductionmentioning

confidence: 99%

Leakage power reduction for coarse-grained dynamically reconfigurable processor arrays using Dual Vt cells

Hirai

Kato

Saito

et al. 2009

2009 International Conference on Field-Programmable Technology

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One of benefit of coarse-grained dynamically reconfigurable processor arrays (DRPAs) is their low dynamic power consumption by operating a number of processing element (PE) in parallel with a low frequency clock. However, in the future advanced process, the leakage power will occupy a considerable part of the total power consumption, and it may degrade the advantage of DRPAs. In order to reduce the leakage power of DRPA without severe performance degradation, eight designs (Mult, Sw, MultSw, LowHalf, 1Row, ColHalf, Sw+Half and Sw+Mult) using Dual-Vt cells are evaluated based on a prototype DRPA called MuCCRA-3T. Evaluation results show that Sw in which Low-Vt cells are only used in switching elements of the array achieved the best power-delay product. If performance of Sw is not enough, Sw+Half in which Low-Vt cells are used for a lower half PEs and all switching elements improves 24% of the leakage power with 5%-14% of extra delay time of the design with all Low-Vt cells.978-1-4244-4377-2/09/$25.00

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“…The new industrial platform is commonly called structured ASIC or hybrid-FPGA structures and is pursued by large semiconductor companies, CAD houses, and start-ups [4,5,7,9,12,15,17,18]. Academic researchers often refer to this implementation platform as regular fabrics and have focused their efforts mainly on either defining the structure of the fabric or exploring how the physical design is impacted by the emerging implementation platforms [2,6,7,8,11,13,14].…”

Section: Introductionmentioning

confidence: 99%

Flexible ASIC

Wong¹,

Kourshanfar

Potkonjak³

2005

Proceedings of the 42nd Annual Conference on Design Automation - DAC '05

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ASIC provides more than an order of magnitude advantage in terms of density, speed, and power requirement per gate. However, economic (cost of masks) and technological (deep micron manufacturability) trends favor FPGA as an implementation platform. In order to combine the advantages of both platforms and alleviate their disadvantages, recently a number of approaches, such as structured ASIC/regular fabrics, have been proposed. Our goal is to introduce an approach that has the same objective, but is orthogonal to those already proposed. The idea is to implement several ASIC designs in such a way that they share the datapath, memory structure, and several bottom layers of interconnect, while each design has only a few unique metal layers. We identified and addressed two main problems in our quest to develop a CAD flow for realization of such designs. They are: (i) the creation of the datapath, and (ii) the identification of common and unique interconnects for each design. Both problems are solved optimally using ILP formulations. We assembled a design flow platform using two new programs and the Trimaran and Shade tools. We quantitatively analyzed the advantages and disadvantages of the approach using the Mediabench benchmark suite.

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Designing mega-ASICs in nanogate technologies

Cited by 10 publications

References 25 publications

Trade-off analysis of fine-grained power gating methods for functional units in a CPU

Trade-off analysis of fine-grained power gating methods for functional units in a CPU

Leakage power reduction for coarse-grained dynamically reconfigurable processor arrays using Dual Vt cells

Flexible ASIC

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