Designing multi-socket systems using silicon photonics

Beamer, Scott; Asanović, Krste; Batten, Christopher; Joshi, Ajay; Stojanović, Vladimir

doi:10.1145/1542275.1542360

Cited by 12 publications

(2 citation statements)

References 9 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Table III shows the setup for the electronic part (intra-chip and inter-chip p2p links in the electronic baseline). Electronic energy parameters shown in this table are derived by DSENT tool [30] and from [31]. The hubs, introduced in Section III, are switches interfacing the intra-cluster networks with the intercluster one.…”

Section: A Simulation and Evaluation Methodologymentioning

confidence: 99%

Boosting multi-socket cache-coherency with low-latency silicon photonic interconnects

Grani

Hendry

Bartolini

et al. 2015

2015 International Conference on Computing, Networking and Communications (ICNC)

View full text Add to dashboard Cite

Speed-up in computing systems today is most often accomplished by increasing parallelism in both hardware and software. Parallel applications residing wholly on a single multicore chip generally utilize implicit inter-thread communication via shared memory managed by cache-coherency mechanisms. However, increasing parallelism by creating coherent domains across many chips poses new challenges. In this work, we illustrate the sensitivity of various applications on a theoretical four-socket system to the latency of their coherency traffic, and show that current solutions, such as Quick Path Interconnect (QPI) and HyperTransport (HT), could benefit greatly from a lower latency communication medium. Then, we propose a silicon photonic inter-chip network that achieves very low-latency and falls within a reasonable power budget.

show abstract

Section: A Simulation and Evaluation Methodologymentioning

confidence: 99%

Boosting multi-socket cache-coherency with low-latency silicon photonic interconnects

Grani

Hendry

Bartolini

et al. 2015

2015 International Conference on Computing, Networking and Communications (ICNC)

View full text Add to dashboard Cite

show abstract

“…The integration of photonics and CMOS electronics has been an active area of research in recent years [1][2][3][4][5][6][7]. With cloud based computing driving the production of larger and more bandwidth intensive data centers as well as the increasing number of processors in multi-core CPUs, the need for more energy efficient and higher bandwidth density communication links between CPUs and RAM has motivated research into photonic CPU-memory communication links [8,9] and the first generation of monolithic electronics-photonics integration [5][6][7]. Photonic communication links, using wavelength division multiplexing (WDM), have the potential to greatly increase the bandwidth density and energy efficiency compared to electrical links [10].…”

Section: Introductionmentioning

confidence: 99%

Efficient wavelength multiplexers based on asymmetric response filters

Wade¹,

Popović²

2013

Opt. Express

View full text Add to dashboard Cite

We propose integrated photonic wavelength multiplexers based on serially cascaded channel add-drop filters with an asymmetric frequency response. By utilizing the through-port rejection of the previous channel to advantage, the asymmetric response provides optimal rejection of the adjacent channels at each wavelength channel. We show theoretically the basic requirements to realize an asymmetric filter response, and propose and evaluate the possible implementations using coupled resonators. For one implementation, we provide detailed design formulas based on a coupled-mode theory model, and more generally we provide broad guidelines that enumerate all structures that can provide asymmetric passbands in the context of a pole-zero design approach to engineering the device response. Using second-order microring resonator filter stages as an example, we show that the asymmetric multiplexer can provide 2.4 times higher channel packing (bandwidth) density than a multiplexer using the same order stages (number of resonators) using conventional all-pole maximally-flat designs. We also address the sensitivities and constraints of various implementations of our proposed approach, as it affects their applicability to CMOS photonic interconnects.

show abstract