Designing of AES Algorithm using Verilog

Soumya, V.; Neelagar, Mahesh B.; Kumaraswamy, K V

doi:10.1109/i2ct42659.2018.9058322

Cited by 5 publications

(1 citation statement)

References 7 publications

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“…This section will show the AES-384 and AES-512 hardware description language [19][20][21][22] simulation process, mainly AES-384/512 for explanation, only with AES-384/512 attached to each process of the demonstration diagram [23][24][25], and not attached versions of AES-128, AES-192, or AES-384. The test content is "Learn to walk before you run".…”

Section: Hardware Description Language Simulationmentioning

confidence: 99%

Maintaining Secure Level on Symmetric Encryption under Quantum Attack

et al. 2023

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Quantum computing is currently being researched in many countries, and if implemented in the near future, it may pose a threat to existing encryption standards. In the quantum computer environment, asymmetric encryption can be solved by Shor’s Algorithm in polynomial time, and the difficulty of breaking symmetric encryption using brute force is reduced from N times to square root N times by Grover’s Algorithm. We take the Advanced Encryption Standard as the theme and increase the key length from the original standard 192 bits and 256 bits to 384 bits and 512 bits, respectively, in order to maintain the security level of AES 192/256 under the environment of quantum computing, so we propose the key schedule of AES 384/512, and write the software in C++ on FPGA. The experimental results show that our scheme can achieve Level III and Level V security levels in a quantum computer attack environment. In addition to increasing the length of the key, we use the LUT method in the process of writing SubBytes to replace the array and speed up the computation to optimize the execution speed. In addition, the proposed scheme is still based on 128-bit computing blocks, rather than computing blocks in larger blocks.

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Section: Hardware Description Language Simulationmentioning

confidence: 99%

Maintaining Secure Level on Symmetric Encryption under Quantum Attack

et al. 2023

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Adaptive Counter Clock Gated S-Box Transformation Based AES Algorithm of Low Power Consumption and Dissipation in VLSI System Design

Subramanian¹,

Venkatachalam²,

Saroja³

2021

J. Phys.: Conf. Ser.

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Advanced Encryption Standard (AES) is an effective algorithm trending today. According to the key length, it works efficiently. Here three types of key lengths are used such as 128, 192, and 256 bits. This paper introduced an Adaptive Counter-Clock (ACC) S-Box algorithm. This algorithm rectifies the error during data encryption and secure data from hackers. In this paper, we have done power consumption, power dissipation, and reduced the area size. Field Programmable Gate Array (FPGA) is utilized for hardware execution in the encryption process. Inverse Mix Column, Inverse Sub Bytes (S-Box) and Inverse Shift Row stages takes place in the decryption, so that the receiver can read the message in plain text which was sent by the sender. For this the receiver should have the same key used by the sender for encryption process. RTL coding is done using Verilog HDL, Xilinx ISE 14.7 FPGA will be used in the implementation.

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Advanced Encryption Standard Algorithm with Optimal S-box and Automated Key Generation

Gupta

Agrawal

2022

2022 2nd International Conference on Advance Computing and Innovative Technologies in Engineering (ICACITE)

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Designing of AES Algorithm using Verilog

Cited by 5 publications

References 7 publications

Maintaining Secure Level on Symmetric Encryption under Quantum Attack

Maintaining Secure Level on Symmetric Encryption under Quantum Attack

Adaptive Counter Clock Gated S-Box Transformation Based AES Algorithm of Low Power Consumption and Dissipation in VLSI System Design

Advanced Encryption Standard Algorithm with Optimal S-box and Automated Key Generation

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