Designing optimized pipelined global interconnects: Algorithms and methodology impact

Abstract

As across-chip wire delays exceed a clock cycle, interconnect pipelining becomes essential. However, the arbitrary insertion of flip-flops can change the differentials of latencies along paths in the circuit, and this can cause the implemented circuit to have a different functionality than was intended by the designer. Although it is possible to use design techniques that maintain the functionality of the circuit, an additional concern is a reduction in the throughput. This may be overcome by careful choices at various stages of design that impact the across-chip wire latencies. This paper surveys the published work on wire-pipelining, describes its impact on circuit as well as system level throughput, and outlines some of the problems to be resolved in formulating a wirepipelining centric strategy for physical design.

Time diversity approach for intra-chip RF/wireless interconnect systems

“…One alternative is to provide a slower clock for the sequential elements latching signals from global wires, whose delays exceed system clock period. However, the practicality of this approach is challenged by increased clock routing complexity, and accomplishing synchronization between the clock domains [3]. Another approach is to adopt Latency Insensitive (LIS) [4] methodology, and a related approach, Globally Asynchronous Locally Synchronous (GALS) [5], uses handshake protocols for inter-module communication.…”

Analysis of Power Consumption and BER of Flip-flop Based Interconnect Pipelining

“…In fact, since the feature size of CMOS devices is continuously decreasing and more functionality is integrated on a chip, the length and number of global interconnects tend to increase [7]. Consequently, in future nanometer designs it will be impossible to carry signal across the chip within a single clock cycle and multi-cycle cross-chip communication becomes necessary, so that cross-chip interconnect is removed from all the timing constraints, and the chip speed is determined by the most critical intra-block/local combinational path, in order to continue employing higher frequencies [4], [5]. Insertion of sequential elements in interconnects lines -a concept that has become known as interconnect pipelining − is one feasible solution for modern nanometer technologies.…”

“…A bunch of work can be found at the architecture level. There is a detailed study of the issue that wire pipelining will alter the function or cycle behavior of a circuit in [4]. Several approaches have been proposed to solve this problem, such as wire retiming [8], algorithm working at the gate level [9] and latency insensitive technique [10].…”

Bit Error Rate Analysis for Flip-flop and Latch Based Interconnect Pipelining

“…Consequently, in nanometer designs it is impossible to carry signal across the chip in a single clock cycle, thus limiting the maximum frequency. The scenario that single-cycle full chip communication will no longer be possible has caused researchers to look into alternative design methodologies that will enable multi-cycle cross-chip communication, so that cross-chip interconnect is removed from all the timing constraints, and the chip speed is determined by the most critical intra-block/local combinational path, in order to continue employing higher frequencies [3], [4].…”

“…For interconnect delays beyond the capabilities of repeater insertion, several alternative approaches can be adopted to meet certain timing constraint [1] [3][5] [6]. But all these approaches have their own drawbacks.…”