Designing optimum one-level carry-skip adders

Kantabutra, Vitit

doi:10.1109/12.277297

Cited by 39 publications

(11 citation statements)

References 9 publications

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“…In addition, due to the small number of transistors, the CSKA benefits from relatively short wiring lengths as well as a regular and simple layout [8][9][10]. In this paper, we have implemented a complementary multiplexer as a skip logic using TANNER EDA tool for high speed and low power application of a 4 bit carry skip adder.…”

Section: Introductionmentioning

confidence: 99%

Design of A High Speed And Low Power 4 Bit Carry Skip Adder

Nagori¹

2017

IJERA

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This paper focuses on carry skip adder (CSKA) structure that has a higher speed yet lower power consumption compared with the conventional one. The speed enhancement is achieved by applying Transmission gate logic (TG) to improve the efficiency of the conventional CSKA structure. The CMOS multiplexer in Conventional CSKA is replaced by multiplexer using transmission gate for the skip logic in proposed CSKA. The structure may be realized with transmission gate multiplexer that improves the speed and delay parameters of the adder. The simulation of this CSKA is done using TANNER EDA. Finally, a low power and high speed proposed structure is implemented, which lowers the power consumption without considerably impacting the speed. The proposed structures are assessed by comparing their speed, power, and delay parameters with those of other existing adders using a 45-nm CMOS technology for a wide range of supply voltages.

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Section: Introductionmentioning

confidence: 99%

Design of A High Speed And Low Power 4 Bit Carry Skip Adder

Nagori¹

2017

IJERA

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“…1. Some techniques for speeding up CSA adders by using variable-size blocks and/or inside-block carry skipping circuits were proposed in [8], [9]; however, their complexity and non-modularity would consume high power and, therefore, have high energy (in spite of low delay) at low voltages.…”

Section: Introductionmentioning

confidence: 99%

Design of an energy-efficient 32-bit adder operating at subthreshold voltages in 45-nm CMOS

Tran

Baas

2010

International Conference on Communications and Electronics 2010

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Abstract-Low-power circuits have been quickly increasing their importance due to the high cost in design of cooling systems with complex chip packaging techniques, and also due to the low energy consumption requirement of portable devices powered by a limited battery capacity. This paper presents the design of a low-power 32-bit adder that is a basic functional unit in most computational platforms. Its energy efficiency is highly achieved while operating in the subthreshold regime.

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“…Carry skip adders, which have O(n) area and O(n 1/2 ) delay provide a good compromise in terms of area and delay, along with a simple and regular layout [6] . Carry skip adders also dissipate less power than other adders due to their low transistor counts and short wire lengths [3,4].…”

Section: Introductionmentioning

confidence: 99%

“…Several studies have been performed to reduce the delay of carry-skip adders [6][7][8][9][10]. Techniques presented in [6,7] select variable block sizes to minimize the delay of adders that use a single level of carry skip logic.…”

Section: Introductionmentioning

confidence: 99%