19th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2004. DFT 2004. Proceedings.
DOI: 10.1109/dftvs.2004.1347832
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Designs for reducing test time of distributed small embedded SRAMs

Abstract: This paper proposes a test architecture aimed at reducing test time of distributed small embedded SRAMs (e-SRAMs). This architecture improves the one proposed in [4,5]. The improvements are mainly two-fold. On one hand, the testing of time-consuming Data Retention Faults (DRFs), that is neglected by the test architecture in [4,5], is now considered and performed via a DFT technique referred to as the "No Write Recovery Test Mode (NWRTM)". On the other hand, a parallel Local Response Analyzer (LRA), instead of … Show more

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