Detailed electrical and reliability study of tapered TSVs

Abstract

This paper investigates the TSV's tapering effect, an inevitable byproduct of the non-ideal Dry Reactive Ion Etching based manufacturing, and its impact on the TSV's electrical performance and reliability properties. For TSV's electrical performance, we show that the TSV delay (estimated by the Elmore model) is not bidirectionally symmetric for a tapered TSV. For TSV's reliability property, current density, thermal mechanical stress, and TSV heating are primary concerns in this paper. We show that the current density and thermal mechanical stress distribution inside the TSV are more nonuniform in realistic tapered TSVs than ideal cylindrical TSVs, both of which lead to faster material fatigue as well as severe electromigration. However, the TSV tapering effect helps us save significant routing areas on the narrower side of the TSV because less Keep Out Zone (KOZ) is needed. The overheating problem becomes significant in 3D-ICs mainly because the oxide layer and bonding materials are usually very poor heat conductors. Furthermore, we set up coupled mass transport equations to estimate TSV's electromigration, based on the current and stress simulation, and produce a MTTF (Mean Time to Failure) map of all positions in TSVs and neighboring areas and this helps us easily recognize the most vulnerable positions in a 3D structure, which could be further optimized during manufacturing and design.Finally, we show our tapered TSV simulations' implications on TSV's modeling, clock network design, and algorithms for gate placement and wire routing. The compact TSV's model and clock network design must take into account the tapering effect, given that signals delay in one direction is significantly slower than the other direction. Cell placement and routing algorithms should treat TSV as obstacles, with different sizes on the top and the bottom layers.

Capacitance Expressions and Electrical Characterization of Tapered Through- Silicon Vias for 3-D ICs

“…The errors may be from the equations of RLGC. The PEs of (15) and (16) are about 6% and 8% for ac, respectively [20], and those of the two capacitances in this paper are less than 1.86% and 3.75%, respectively.…”

“…In [15], closed-form formulas for resistance and inductance of coaxial TSVs considering skin effect and eddy effect were proposed. Besides, research on the T-TSV has also been performed since tapering effect is inevitable in the deep reactive ion etch process [16]. Also, many benefits of tapering effect have been reported, such as better manufacturability [17], [18], less keep out zone [16], and better counterbalance of power and thermal distribution in 3-D-ICs [19].…”

“…Besides, research on the T-TSV has also been performed since tapering effect is inevitable in the deep reactive ion etch process [16]. Also, many benefits of tapering effect have been reported, such as better manufacturability [17], [18], less keep out zone [16], and better counterbalance of power and thermal distribution in 3-D-ICs [19]. Closed-form expressions were proposed to calculate the resistance and inductance of different profiles of TSVs in [20].…”

“…15 plots the RC time constant τ RC and L/R time constant τ L/R of the T-TSV and C-TSV S-G pairs calculated using (8),(13), and (14)-(16). C sub is in series with…”