Detecting memory faults in the presence of bit line coupling in SRAM devices

Irobi, Sandra; Al-Ars, Zaid; Hamdioui, Said

doi:10.1109/test.2010.5699246

Cited by 16 publications

(14 citation statements)

References 16 publications

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“…from the target cell [14]. The effect can be described as follows: if the target cell contains a logic 1 and the adjacent cell also contains a logic 1, the target cell is considered stressed and may be read as a 0.…”

Section: Methodsmentioning

confidence: 99%

Approximate computation with outlier detection in Topaz

Achour

Rinard

2015

SIGPLAN Not.

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We present Topaz, a new task-based language for computations that execute on approximate computing platforms that may occasionally produce arbitrarily inaccurate results. Topaz maps tasks onto the approximate hardware and integrates the generated results into the main computation. To prevent unacceptably inaccurate task results from corrupting the main computation, Topaz deploys a novel outlier detection mechanism that recognizes and precisely reexecutes outlier tasks. Outlier detection enables Topaz to work effectively with approximate hardware platforms that have complex fault characteristics, including platforms with bit pattern dependent faults (in which the presence of faults may depend on values stored in adjacent memory cells). Our experimental results show that, for our set of benchmark applications, outlier detection enables Topaz to deliver acceptably accurate results (less than 1% error) on our target approximate hardware platforms. Depending on the application and the hardware platform, the overall energy savings range from 5 to 13 percent. Without outlier detection, only one of the applications produces acceptably accurate results.

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Section: Methodsmentioning

confidence: 99%

Approximate computation with outlier detection in Topaz

Achour

Rinard

2015

SIGPLAN Not.

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“…An analytical evaluation of the CC BL effect is presented in [3][4] [5]. The analysis is based on a 3x3 memory cell array which was designed using the transistor models of the 65nm BSIM4 spice model.…”

Section: Modeling Of Bit Line Coupling Capacitancesmentioning

confidence: 99%

“…Figure 1. SRAM electrical Spice model [4] [5] Considering the read operation, it has been shown in [3][4] [5] that the coupling capacitance Cb causes neighboring BLs to have an influence on the voltage development only when reading from a cell. This effect can impact the proper sense amplifier operation, which results in an incorrect read data (while the stored value is still correct).…”

Section: Modeling Of Bit Line Coupling Capacitancesmentioning

confidence: 99%

“…A complete study on the influence of CC BL and neighborhood data on the read operation, for any possible spot defect, has been presented in [5]. Owning to electrical simulations, authors show that CC BL can induce extra stress when reading from memory cells in presence of spot defects.…”

Section: Introductionmentioning

confidence: 99%

“…It guarantees the detection of all single-cell static faults both in presence and in absence of CC BL for any possible open defect. In [5], a march test m-MSS of a 108N complexity is presented. The March m-MSS is able to detect all single-cell and two-cell static faults, with and without CC BL for any possible spot defect.…”

Section: Introductionmentioning

confidence: 99%

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Optimized march test flow for detecting memory faults in SRAM devices under bit line coupling

Zordan

Bosio

Dilillo

et al. 2011

14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems

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A comprehensive SRAM test must guarantee the correct functioning of each cell of the memory (ability to store and to maintain data), and the corresponding addressing, write and read operations. SRAM testing is mainly based on the concept of fault model used to mimic faulty behaviors. Traditionally, the effects of bit line coupling capacitances have not been considered during the fault analysis. However, recent works show the increasing impact of bit line coupling capacitances on the SRAM behavior. This paper reviews and discusses preview works addressing the issues coming from bit line parasitic capacitances and data contents on SRAM testing, pointing out the impacts of these effects on the existing test solutions. Then, we introduce two optimizations of the state-ofthe-art test solution able to take into account the influence of bit line coupling capacitances while reducing the test length of about 60% and 80%, respectively.

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Efficient Resistive Defect Detection Technique for Performance Enhancement of Static Random Access Memory

Tak

Mali

2021

Lecture Notes in Electrical Engineering

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Detecting memory faults in the presence of bit line coupling in SRAM devices

Cited by 16 publications

References 16 publications

Approximate computation with outlier detection in Topaz

Approximate computation with outlier detection in Topaz

Optimized march test flow for detecting memory faults in SRAM devices under bit line coupling

Efficient Resistive Defect Detection Technique for Performance Enhancement of Static Random Access Memory

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