Detecting phases in parallel applications on shared memory architectures

Perelman, Erez; Polito, Marzia; Bouguet, J.-Y.; Sampson, John J.; Calder, Brad; Dulong, Carole

doi:10.1109/ipdps.2006.1639325

Cited by 48 publications

(50 citation statements)

References 29 publications

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“…Many applications exhibit inherent periodicity or phase behavior [18], [20]. Figure 3 plots the IPC variation through time of one of the eight threads for the class A input set of the N-ft benchmark from the NAS Parallel Benchmarks (NPB) suite.…”

Section: A the Effect Of Periodicity On Samplingmentioning

confidence: 99%

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Sampled simulation of multi-threaded applications

Carlson

Heirman

Eeckhout

2013

2013 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS)

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Abstract-Sampling is a well-known workload reduction technique that allows one to speed up architectural simulation while accurately predicting performance. Previous sampling methods have been shown to accurately predict single-threaded application runtime based on its overall IPC. However, these previous approaches are unsuitable for general multi-threaded applications, for which IPC is not a good proxy for runtime. Additionally, we find that issues such as application periodicity and inter-thread synchronization play a significant role in determining how best to sample these applications.The proposed multi-threaded application sampling methodology is able to derive an effective sampling strategy for candidate applications using architecture-independent metrics. Using this methodology, large input sets can now be simulated which would otherwise be infeasible, allowing for more accurate conclusions to be made than from studies using scaled-down input sets. Through the use of the proposed methodology, we can simulate less than 10% of the total application runtime in detail. On the SPEComp, NPB and PARSEC benchmarks, running on an 8-core simulated system, we achieve an average absolute error of 3.5%.

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Section: A the Effect Of Periodicity On Samplingmentioning

confidence: 99%

“…Perelman et al [18] cluster multi-threaded applications by looking at each thread in isolation. They predict the IPC and cache hit rates of clustered application phases, but do not evaluate runtime error.…”

Section: B Multi-threaded Samplingmentioning

confidence: 99%

Sampled simulation of multi-threaded applications

Carlson

Heirman

Eeckhout

2013

2013 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS)

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“…Our logging and simulation approach allows selecting the regions to checkpoint manually, or using techniques such as systematic sampling [16], [15] or Simpoint [12], [11]. The focus of this paper is not on picking samples, but to show that the samples can be simulated deterministically for design space exploration.…”

Section: Picking Samples For Simulationmentioning

confidence: 99%

“…Perelman et al [11] proposed a phase guided technique for selecting simulation regions for multi-threaded programs. They do not deal with the non-determinism problem in their Fig .…”

Section: B Simulation Sampling Of Multi-threaded Workloadsmentioning

confidence: 99%

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Reproducible simulation of multi-threaded workloads for architecture design exploration

Pereira

Patil

Calder

2008

2008 IEEE International Symposium on Workload Characterization

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Communication Based Proactive Link Power Management

Muralidhara

Kandemir

2009

High Performance Embedded Architectures and Compilers

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International audienceAs the number of cores in CMPs increases, NoC is projected to be the dominant communication fabric. Increase in the number of cores brings an important issue to the forefront, the issue of chip power consumption, which is projected to increase rapidly with the increase in number of cores. Since NoC infrastructure contributes significantly to the total chip power consumption, reducing NoC power is crucial. While circuit level techniques are important in reducing NoC power, architectural and software level approaches can be very effective in optimizing power consumption. Any such technique power saving technique should be scalable and have minimal adverse impact on performance. We propose a dynamic, communication link usage based, proactive link power management scheme. This scheme, using a Markov model, proactively manages communication link turn-ons and turn-offs, which results in negligible performance degradation and significant power savings. We show that our prediction scheme is about 98% accurate for the SPEC OMP benchmarks and about 93% over all applications experimented. This accuracy helps us achieve link power savings of up to 44% and an average link power savings of 23.5%. More importantly, it incurs performance penalties as low as 0.3% on average

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Detecting phases in parallel applications on shared memory architectures

Abstract: Abstract

Cited by 48 publications

References 29 publications

Sampled simulation of multi-threaded applications

Sampled simulation of multi-threaded applications

Reproducible simulation of multi-threaded workloads for architecture design exploration

Communication Based Proactive Link Power Management

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