Detection with built-in error correction for d=1 constrained channels

Krachkovsky, V.Yu.

doi:10.1109/intmag.2000.872462

Cited by 1 publication

(2 citation statements)

References 4 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Further, at high data-rates, implementation of the detector, whose complexity tends to increase for high performance, becomes a serious concern. The multilevel decision feedback equalization (MxDFE) family of detectors (viz., MDFE, M2DFE, M3DFE, and M4DFE), which uses the run-length-limited (RLL) rate 2/3 (1, 7) code, has been shown to offer viable solutions to overcome most of these problems [3]- [5], [13]. Because the minimum spacing between transitions is increased by the code constraint, the transition density dependent artifacts are less serious in (1, 7)-coded channels compared with (0, )-coded channels.…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

A novel interpolation approach for reducing clock-rate in multilevel decision feedback equalization detectors

et al. 2000

View full text Add to dashboard Cite

The multilevel decision feedback equalization (MxDFE) family of detectors provides excellent performance over (1, 7)-coded magnetic recording channels, while being simple in structure. However, the reduced code-rate of 2/3 increases the channel data rate by 50% compared to the user data rate. Although this is not a problem for the write heads because of the reduced bandwidth of the (1, 7) writing signal [compared with (0, ) codes], it becomes an issue at the detector side for highdata-rate applications. We propose a novel interpolation approach for reducing the detector clock rate. Performance simulations of MDFE and M2DFE detectors, carried out over different user densities, channel models, and equalizer configurations, show that the proposed scheme can reduce the detector clock rate to the user rate with negligible impact on performance. We also present a timing recovery scheme for acquisition and tracking of the reduced-rate clock.

show abstract

Section: Introductionmentioning

confidence: 99%

“…Further, the bandwidth of the (1, 7) writing signal is significantly smaller, thus, making it writing friendly [3]. Moreover, the design of MxDFE detectors exploiting the constraint and incorporating certain novel and advanced features helps to attain performance that is close to optimum [5], [13].…”

Section: Introductionmentioning

confidence: 99%