Determination of Manufacturing Resurf Process Window for a Robust 700V Double Resurf LDMOS Transistor

Hossain, Z.

doi:10.1109/ispsd.2008.4538916

Cited by 13 publications

(3 citation statements)

References 5 publications

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“…Since the integrated doping concentration in the P-top and N-drift regions is relatively low (1-3 × 10 12 cm −2 ), these devices are susceptible to surface charges in dielectrics, passivation, and molding compounds, particularly during high-temperature reverse-bias (HTRB) reliability testing [17] (Chap. 11).…”

Section: (D) Charge Balancementioning

confidence: 99%

High-Voltage and Power Transistors

El-Kareh¹,

Hutter²

2015

Silicon Analog Components

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This chapter focuses mainly on the drain-extended MOS transistor, DEMOS, for high voltage applications, and on the lateral double-diffused MOS transistor, LDMOS, for high power applications. In both cases, the drain is extended with a lightly-doped region, referred to as the drift region, to sustain the high voltage. The chapter begins with an analysis of the drift region and its optimization, typically by reduced surface-field (RESURF) techniques. The transistor switching performance is then analyzed, followed by a discussion of DEMOS and LDMOS design considerations and characteristics. High-voltage and high-current effects are then described, including quasi-saturation, body current, on-state breakdown, and safe operating area (SOA). The chapter concludes with selected high-voltage device applications. IntroductionThe MOSFETs discussed in Chap. 6 are designed for digital, analog, mixed-signal, and RF applications that operate in the low-to-medium voltage range of about 0.8-6 V. Many analog applications, however, require transistors that can handle voltages above 20 V and currents in the ampere range. Those transistors are referred to as high-voltage and power transistors. This chapter provides a comprehensive analysis of the drain-extended MOS transistor (DEMOS), for high-voltage and low-current applications, and the lateral double-diffused MOS (LDMOS) transistor, LDMOS, for power applications. (The "D" in LDMOS describes the sequential (double) diffusion of boron and arsenic through the same oxide opening, defining a precise channel length (Chap. 9). The "L" means that the current path is parallel to the silicon surface (lateral), as opposed to "V" in VDMOS where the current is nearly vertical to the silicon surface.) Schematic cross sections of both transistors (Table 7.1). The DEMOS is typically processed without added process complexity, whereas the LDMOS requires optimization of the P-body and N-drift regions to achieve high voltages and currents while minimizing the drain-to-source resistance and transistor area.The interest in bipolar, CMOS, and DMOS (BCD) technologies has been driven primarily by the proliferation of portable electronics, automotive electronics, and the need for energy efficiency. These applications cluster around different operating points, with 24 V for portable electronics; 60 V for automotive, solar, and LED backlighting; 85 V for power over Ethernet; 120 V for telecommunication; and 700 V for offline LED lighting, consumer, and industrial applications. As a result, BCD is now the technology of choice to realize power ICs by most integrated device manufacturers (IDM) and foundries [1][2][3][4][5].This chapter focuses mainly on transistors with voltage capabilities in the range of 20-700 V, where the bulk of the product applications lie.

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Section: (D) Charge Balancementioning

confidence: 99%

High-Voltage and Power Transistors

El-Kareh¹,

Hutter²

2015

Silicon Analog Components

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“…But the performance of this class of devices is sensitive to the optimum charge balance in the drift region, which is in general at the silicon surface, and thus it is strongly impacted by mobile charges accumulated in the overlying isolation and mold-compound passivation on top [5]. For this reason, additional metal and/or poly-silicon field-plates and floating-rings are required to stabilize the surface electric field [6,7], even if they might limit the maximum intrinsic performance of the device. The understanding of mobile charge transport at the molding compound surface is thus of primary importance to improve the power device performance and reliability at the design stage.…”

Section: Introductionmentioning

confidence: 99%

Electrical characterization of epoxy-based molding compounds for next generation HV ICs in presence of moisture

Cornigli

Reggiani

Gnudi

et al. 2018

Microelectronics Reliability

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“…In the published research results for 500 V and higher voltage NLDMOS, some researches refer to the devices structure with field plate [9][10][11]. However, in-depth study of metal and polysilicon field plate on such high voltage NLDMOS is still needed for further investigation.…”

Section: Introductionmentioning

confidence: 99%

The Investigation of Field Plate Design in 500 V High Voltage NLDMOS

Liu¹,

Xu²,

Jiang³

et al. 2015

Advances in Condensed Matter Physics

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This paper presents a 500 V high voltage NLDMOS with breakdown voltage (VBD) improved by field plate technology. Effect of metal field plate (MFP) and polysilicon field plate (PFP) on breakdown voltage improvement of high voltage NLDMOS is studied. The coeffect of MFP and PFP on drain side has also been investigated. A 500 V NLDMOS is demonstrated with a 37 μm drift length and optimized MFP and PFP design. Finally the breakdown voltage 590 V and excellent on-resistance performance (Rsp= 7.88 ohm * mm2) are achieved.

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Determination of Manufacturing Resurf Process Window for a Robust 700V Double Resurf LDMOS Transistor

Cited by 13 publications

References 5 publications

High-Voltage and Power Transistors

High-Voltage and Power Transistors

Electrical characterization of epoxy-based molding compounds for next generation HV ICs in presence of moisture

The Investigation of Field Plate Design in 500 V High Voltage NLDMOS

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