Determination of stress in shallow trench isolation for deep submicron MOS devices by UV Raman spectroscopy

Dombrowski, K. F.; Fischer, A.; Dietrich, B.; Wolf, Ingrid De; Bender, H.; Pochet, Sylvie; Simons, V.; Rooyackers, R.; Badenes, G.; Stuer, C.; Landuyt, J. van

doi:10.1109/iedm.1999.824169

Cited by 11 publications

(4 citation statements)

References 5 publications

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“…Table III reports the stress limits of these regions as estimated from the comparison between the simulation results and the electrical tests of the transistor array dislocation monitor structures. As expected (31), the developed stress is lower in "wide" than in "narrow" structures. In addition, the limit values in table III are significantly lower than the upper yield stress data reported for instance in (30).…”

Section: Experimental and Modeling Resultssupporting

confidence: 83%

(Invited) Defect Generation in Device Processing and Impact on the Electrical Performances

et al. 2013

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This paper collects the results of some experiments aimed at investigating the physical mechanisms of defect generation in devices. It is shown that suitable limits for the mechanical stress can be defined to prevent defect generation. In addition, a high temperature stress release annealing can be beneficial for stress reduction and defect prevention. The annealing of implanted layers may result in crystal defect formation even with no contribution from mechanical stress. In this case, the silicon surface plays a relevant role in reducing the point defect concentration and hence the nucleation of extended defects. In the annealing process of high energy implantations, the most damaged region is far from the wafer surface. Under these conditions, impurities in the silicon substrate play a relevant role in determining the resulting defect morphology. The presence of interstitial oxygen forces defects to grow along <110> directions parallel to the silicon surface, thus preventing them to reach the device region.

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Section: Experimental and Modeling Resultssupporting

confidence: 83%

(Invited) Defect Generation in Device Processing and Impact on the Electrical Performances

et al. 2013

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“…Table VII reports the stress limits of these regions as estimated from the comparison between the simulation results and the electrical tests of the transistor array dislocation monitor structures. As expected (19), the developed stress is lower in "large" than in "small" structures. However, the limit values too are lower in the "large" than in the "small" structures, so the smallest structure is not necessarily the most critical for defect generation.…”

Section: Modeling-experiments Comparisonsupporting

confidence: 83%

Mechanical Stress and Defect Formation in Device Processing

Polignano¹,

Carnevale²,

Fantini³

et al. 2006

ECS Trans.

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In this work we address the problem of estimating the mechanical stress and the related risk of crystal defect generation in a complex device process. The validity of numerical calculations of the mechanical stress developed in the device process flow is assessed by comparing the simulation results with the electrical measurements of test structures designed to monitor the dislocations formation and of other silicon strain sensitive structures. The results show that based upon numerical calculations it is possible to define mechanical stress criteria for preventing defect generation. By using this sort of criteria, potentially dangerous process variations can be easily identified. This method is quite general and can be applied to any device process flow. On the other hand, by comparing the electrical results of structures prone to defect generation and of stress-sensitive transistors with a non-critical geometry for defect generation, it is shown that after defect nucleation the elastic stress in non-critical structures and the defect-related failure fraction in critical structures may evolve into opposite directions. Therefore, suitable stress criteria are needed at all the levels in the process flow where crystal damage may cause defect nucleation. In this study it is also pointed out that a high temperature stress release annealing can be beneficial for stress reduction and defect prevention, but its position in the process flow is critical.

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“…However, it has been difficult to get a detailed profile of the strain in the very thin layer at the CESL/Si interface. In this study, we measured the strain by high-resolution UV-Raman spectroscopy with expecting the strain field induced by CESL to be near the surface [4]. Furthermore, we investigated the mechanism responsible for introducing strain by comparing the strain before and after SiN patterning.…”

Section: Introductionmentioning

confidence: 99%

Effective Control of Strain in SOI by SiN Deposition

et al. 2007

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Strain introduction in SOI substrates by SiN capping film was evaluated by UV-Raman spectroscopy. Induced strain became larger with increasing SiN film thickness. SOI substrates originally had tensile strain and the SiN cap shifted the strain toward the compressive direction. The induced strain was larger in the thinner SOI substrates with the same thickness of the SiN capping film. We also evaluated a substrate after SiN patterning with a high spatial resolution of 200-nm, and found strain enhancement at the pattern edge.

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Determination of stress in shallow trench isolation for deep submicron MOS devices by UV Raman spectroscopy

Cited by 11 publications

References 5 publications

(Invited) Defect Generation in Device Processing and Impact on the Electrical Performances

(Invited) Defect Generation in Device Processing and Impact on the Electrical Performances

Mechanical Stress and Defect Formation in Device Processing

Effective Control of Strain in SOI by SiN Deposition

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