Deterministic clock gating to eliminate wasteful activity due to wrong-path instructions in out-of-order superscalar processors

Mohyuddin, Nasir; Patel, Kimish; Pedram, Massoud

doi:10.1109/iccd.2009.5413158

Cited by 4 publications

(5 citation statements)

References 8 publications

(8 reference statements)

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“…As indicated on Figure 2, this technique uses the same internal clock-gating circuitry as MaskCG. A similar approach is widely used in scalar processors and is known as Deterministic Clock-Gating [6,7]. Nonetheless, this technique has more potential for power savings than its scalar equivalent as it can benefit from the following vector specific advantages:…”

Section: Idle Unit Clock-gating (Idlecg)mentioning

confidence: 99%

“…Possible values of the number of lanes (n L ) are 1, 2, and 4. In our experiments, we do not examine more lanes as it would not satisfy well a low power core budget 7 . Moreover, values that we choose are typical in vector processor design [29].…”

Section: Vectorsimmentioning

confidence: 99%

“…Clock-gating is a common method to reduce switching power in synchronous pipelines [6,7,8,9,10]. It is practically a standard in low-power design.…”

Section: Introductionmentioning

confidence: 99%

“…Therefore, the conditions under which clock-gating can be applied should be extensively studied and identified. A widely used approach is to clock-gate a whole FU when it is idle [6,7] . E-mail: ivan-srb@live.com, oscar.palomar@gmail.com, stanic.milan@gmail.com, osman.unsal@bsc.es, adrian.cristal@bssc.es, mateo.valero@bsc.es…”

Section: Introductionmentioning

confidence: 99%

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Vector Processing-Aware Advanced Clock-Gating Techniques for Low-Power Fused Multiply-Add

Ratkovic¹,

Palomar

Stanić

et al. 2018

IEEE Trans. VLSI Syst.

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The need for power-efficiency is driving a rethink of design decisions in processor architectures. While vector processors succeeded in the high-performance market in the past, they need a re-tailoring for the mobile market that they are entering now. Floating point fused multiply-add, being a functional unit with high power consumption, deserves special attention. Although clock-gating is a well-known method to reduce switching power in synchronous designs, there are unexplored opportunities for its application to vector processors, especially when considering active operating mode. In this research, we comprehensively identify, propose, and evaluate the most suitable clock-gating techniques for vector fused multiply-add units (VFU). These techniques ensure power savings without jeopardizing the timing. We evaluate the proposed techniques using both synthetic and "real world" application-based benchmarking. Using vector masking and vector multi-lane-aware clock-gating, we report power reductions of up to 52%, assuming active VFU operating at the peak performance. Among other findings, we observe that vector instruction-based clock-gating techniques achieve power savings for all vector floating-point instructions. Finally, when evaluating all techniques together, using "real world" benchmarking, the power reductions are up to 80%. Additionally, in accordance with processor design trends, we perform this research in a fully parameterizable and automated fashion.

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Section: Idle Unit Clock-gating (Idlecg)mentioning

confidence: 99%

Section: Vectorsimmentioning

confidence: 99%

“…Clock-gating is a common method to reduce switching power in synchronous pipelines [6,7,8,9,10]. It is practically a standard in low-power design.…”

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Vector Processing-Aware Advanced Clock-Gating Techniques for Low-Power Fused Multiply-Add

Ratkovic¹,

Palomar

Stanić

et al. 2018

IEEE Trans. VLSI Syst.

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show abstract

“…As indicated on Figure 6.1, this technique uses the same internal clock-gating circuitry as MaskCG. A similar approach is widely used in scalar processors and is known as Deterministic Clock-Gating [68,73]. Nonetheless, this technique has more potential for power savings than its scalar equivalent as it can benefit from the following vector specific advantages:…”

Section: Idle Unit Clock-gating (Idlecg)mentioning

confidence: 99%

On the design of power- and energy-efficient functional units for vector processors

Ratkovic¹

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Vector processors are a very promising solution for mobile devices and servers due to their inherently energy-efficient way of exploiting datalevel parallelism. While vector processors succeeded in the high performance market in the past, they need a re-tailoring for the mobile market that they are entering now. Functional units are a key components of computation intensive designs like vector architectures, and have significant impact on overall performance and power. Therefore, there is a need for novel, vector-specific, design space exploration and low power techniques of vector functional units. We present a design space exploration of vector adder (VA) and multiplier unit (VMU). We examine advantages and side effects of using multiple vector lanes and show how it performs across a broad frequency spectrum to achieve an energy-efficient speed-up. As the final results of our exploration, we derive Pareto optimal design points and present guidelines on the selection of the most appropriate VMU and VA for different types of vector processors according to different sets of metrics of interest. To reduce the power of vector floating-point fused multiply-add units (VFU), we comprehensively identify, propose, and evaluate the most suitable clock-gating techniques for it. These techniques ensure power savings without jeopardizing the performance. We focus on unexplored opportunities for clock-gating application to vector processors, especially in active operating mode. Using vector masking and vector multilane-aware clock-gating, we report power reductions of up to 52%, assuming active VFU operating at the peak performance. Among other findings, we observe that vector instruction-based clock-gating techniques achieve power savings for all vector floating-point instructions. Finally, when evaluating all techniques together, the power reductions are up to 80%. We propose a methodology that enables performing this research in a fully parameterizable and automated fashion using two kinds of benchmarks, synthetic and "real world" application based. For this interrelated circuit-architecture research, we present novel frameworks with both architectural- and circuit-level tools, simulators and generators (including ones that we developed). Our frameworks include both design(e.g. adder's family type) and vector architecture-related parameters (e.g. vector length). Additionally, to find the optimal estimation flow, we perform a comparative analysis, using a design space exploration as a case study, of the currently most used estimation flows: Physical layout Aware Synthesis (PAS) and Place and Route (PnR). We study and compare post-PAS and post-PnR estimations of the metrics of interest and the impact of various design parameters and input switching activity factor (aI).

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Speculative path power estimation using trace-driven simulations during high-level design phase

Chandra

Jayaseelan

Bhargava³

2016

2016 IEEE 34th International Conference on Computer Design (ICCD)

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Deterministic clock gating to eliminate wasteful activity due to wrong-path instructions in out-of-order superscalar processors

Cited by 4 publications

References 8 publications

Vector Processing-Aware Advanced Clock-Gating Techniques for Low-Power Fused Multiply-Add

Vector Processing-Aware Advanced Clock-Gating Techniques for Low-Power Fused Multiply-Add

On the design of power- and energy-efficient functional units for vector processors

Speculative path power estimation using trace-driven simulations during high-level design phase

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