Deterministic sorting and randomized median finding on the BSP model

Gerbessiotis, Alexandros V.; Siniolakis, Constantinos J.

doi:10.1145/237502.237561

Cited by 50 publications

(57 citation statements)

References 16 publications

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“…At the other extreme, the LogP model [9,19] and bulksynchronous parallel (BSP) [10,13,25] model, assume a parallel architecture where each processor has its own internal memory of size at least N/P . In these models there is no shared memory and the inter-processor communication is assumed to occur via message passing through some interconnection network.…”

Section: Introductionmentioning

confidence: 99%

Fundamental parallel algorithms for private-cache chip multiprocessors

Arge

Goodrich

Nelson

et al. 2008

Proceedings of the Twentieth Annual Symposium on Parallelism in Algorithms and Architectures

134

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In this paper, we study parallel algorithms for private-cache chip multiprocessors (CMPs), focusing on methods for foundational problems that can scale to hundreds or even thousands of cores. By focusing on private-cache CMPs, we show that we can design efficient algorithms that need no additional assumptions about the way that cores are interconnected, for we assume that all inter-processor communication occurs through the memory hierarchy. We study several fundamental problems, including prefix sums, selection, and sorting, which often form the building blocks of other parallel algorithms. Indeed, we present two sorting algorithms, a distribution sort and a mergesort. All algorithms in the paper are asymptotically optimal in terms of the parallel cache accesses and space complexity under reasonable assumptions about the relationships between the number of processors, the size of memory, and the size of cache blocks. In addition, we study sorting lower bounds in a computational model, which we call the parallel external-memory (PEM) model, that formalizes the essential properties of our algorithms for private-cache chip multiprocessors.

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Section: Introductionmentioning

confidence: 99%

Fundamental parallel algorithms for private-cache chip multiprocessors

Arge

Goodrich

Nelson

et al. 2008

Proceedings of the Twentieth Annual Symposium on Parallelism in Algorithms and Architectures

134

View full text Add to dashboard Cite

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“…They are often used in conjunction with experimentation to account for aspects that are not considered by the models, such as local computation times. As such, they have been quite successful, leading to practical designs of various algorithms [3], [6], [14], [16], [17], [22], [26], [30], [38].…”

Section: Introductionmentioning

confidence: 99%

Accounting for memory bank contention and delay in high-bandwidth multiprocessors

Blelloch

Gibbons

Matias

et al. 1995

Proceedings of the Seventh Annual ACM Symposium on Parallel Algorithms and Architectures - SPAA '95

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Abstract-For years, the computation rate of processors has been much faster than the access rate of memory banks, and this divergence in speeds has been constantly increasing in recent years. As a result, several shared-memory multiprocessors consist of more memory banks than processors. The object of this paper is to provide a simple model (with only a few parameters) for the design and analysis of irregular parallel algorithms that will give a reasonable characterization of performance on such machines. For this purpose, we extend Valiant's bulk-synchronous parallel (BSP) model with two parameters: a parameter for memory bank delay, the minimum time for servicing requests at a bank, and a parameter for memory bank expansion, the ratio of the number of banks to the number of processors. We call this model the (d, x)-BSP. We show experimentally that the (d, x)-BSP captures the impact of bank contention and delay on the CRAY C90 and J90 for irregular access patterns, without modeling machine-specific details of these machines. The model has clarified the performance characteristics of several unstructured algorithms on the CRAY C90 and J90, and allowed us to explore tradeoffs and optimizations for these algorithms. In addition to modeling individual algorithms directly, we also consider the use of the (d, x)-BSP as a bridging model for emulating a very high-level abstract model, the Parallel Random Access Machine (PRAM). We provide matching upper and lower bounds for emulating the EREW and QRQW PRAMs on the (d, x)-BSP.

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“…It offers the prospect of achieving both scalable parallel performance and architecture independent parallel software and provides a framework which permits the performance of parallel and distributed systems to be analyzed and predicted in a precise way. Since its introduction [19,20], the model has been extensively examined [3,8,9,10,11]. The BSP computer as described in [19] consists of the following three components: (i) a collection of p processor/memory components each component consisting of a sequential processor with a block of local memory, (ii) a communication network that can deliver messages point to point among the components, (iii) and a mechanism for efficient barrier synchronization of all or a subset of the processing units.…”

Section: Introductionmentioning

confidence: 99%

“…These methods fail, however, to deliver optimal performance when implemented on the BSP model of computation. Previously known results on BSP sorting include deterministic [1,9,12] and randomized [8] algorithms. Our sorting algorithm improves upon these approaches in various aspects.…”

Section: Introductionmentioning

confidence: 99%

“…In [1], it is shown that for all values of n and p such that p = On 1, , 0 1 , a version of column-sort [14] provides an upper bound of d ,3:42 eOn lg n=p and d ,3:42 eOgnlg n=p for computation and communication respectively. In [9], an improved upper bound of 1+b ,1 1, c1, =2+o1T seq =p and Ogn=p is shown for computation and communication respectively, where T seq is the time required by sequential sorting. Experimental results indicate that the algorithm is also of practical value.…”

Section: Introductionmentioning

confidence: 99%

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