Developing 13-kV 4H-SiC MOSFETs: Significance of Implant Straggle, Channel Design, and MOS Process on Static Performance

Yun, Nick; Kim, Dong‐Young; Lynch, Justin; Morgan, Adam J.; Sung, Woongje; Kang, Minseok; Agarwal, Anant; Green, Ronald; Lelis, Aivars J.

doi:10.1109/ted.2020.3017150

Cited by 24 publications

(8 citation statements)

References 12 publications

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“…In addition, the impact of lateral straggle of the P + shielding region on the dynamic characteristics of the SiC power MOSFET was not discussed in the previous publications [13] [15]. The analysis presented in this paper shows a substantial reduction in the gate-drain capacitance and the gate-drain charge due to the implant straggle of the P + shielding region that is favorable for obtaining faster transients…”

Section: Introductionmentioning

confidence: 81%

“…It was also pointed out that lateral straggle of the P-well impacts the edge termination performance, an effect that had been previously documented with simulations and experimental results [14]. However, the magnitude of the lateral straggle was not quantified in the paper [13]. The authors state that the straggle of the P-well is significant for their 13 kV devices due to the low drift region doping level, unlike in the case of 1.2 kV SiC power MOSFETs with a JFET width of 1.4 m.…”

Section: Introductionmentioning

confidence: 87%

“…2. The FATFET structure is a lateral MOSFET with a large channel length that is commonly used to extract the inversion or accumulation channel mobility [13,16]. Accumulation channel MOSFETs utilize an N-base region that is completely depleted at zero gate bias by the built-in potential of the junction between the N-base region and the P + shielding region [11].…”

Section: Device Structures and Fabricationmentioning

confidence: 99%

“…The magnitude of the lateral straggle is proportional to the energy used for the ion-implantation. It has recently been reported that lateral straggle of the P-well region has a strong impact on the performance of 13 kV SiC planar-gate power MOSFETs [13]. It was demonstrated that the lateral straggle reduces the width of the JFET region producing an increase in on-resistance and even non-linear on-state characteristics.…”

Section: Introductionmentioning

confidence: 99%

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Implant Straggle Impact on 1.2 kV SiC Power MOSFET Static and Dynamic Parameters

Agarwal

Baliga

2022

IEEE J. Electron Devices Soc.

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Significant impact of the ion-implant straggle of the P + shielding region on the static and dynamic characteristics of 1.2 kV 4H-SiC power MOSFETs is demonstrated in this paper by using analytical and TCAD modelling. The P + region ion-implant straggle not only reduces the JFET width but increases the channel length. This combination is shown to displace a SiC power MOSFET structure optimized without ion-implant straggle away from the optimum JFET width required to achieve the lowest specific on-resistance, resulting in an increase in the specific on-resistance by a factor of 2-3x for the typically used JFET width of 0.7 m. The theoretical analysis is supported by data measured on 1.2 kV SiC power MOSFETs fabricated with channel lengths of 0.3 and 0.5 m using both accumulation and inversion mode channels. The presence of the P + shielding region ion-implant straggle is shown to: (a) increase specific onresistance by 15-30%; (b) suppress short-channel effects; (c) reduce electric field in the gate oxide; (d) reduce the transconductance; (e) reduce saturated drain current; and (f) significantly reduce the gate-drain capacitance and gate charge. Impact of P + shielding region lateral straggle on device cell optimization is an important contribution of this paper.

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Section: Introductionmentioning

confidence: 81%

Section: Introductionmentioning

confidence: 87%

Section: Device Structures and Fabricationmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Implant Straggle Impact on 1.2 kV SiC Power MOSFET Static and Dynamic Parameters

Agarwal

Baliga

2022

IEEE J. Electron Devices Soc.

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“…The devices were fabricated by Analog Devices, Inc. (ADI) fabrication facility in Hillview, San Jose, CA, using the same base process line [19] [20]. A 10 µm thick drift layer with Ntype doping concentration of 8×10 15 cm −3 on 6-inch, N+ 4H-SiC substrate was used for the fabrication of proposed 1.2 kV MOSFETs.…”

Section: Device Fabrication Technologymentioning

confidence: 99%

An Inclusive Structural Analysis on the Design of 1.2kV 4H-SiC Planar MOSFETs

Kim¹,

Yun

Jang

et al. 2021

IEEE J. Electron Devices Soc.

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A detailed structural analysis of 1.2 kV 4H-SiC MOSFETs with accumulation mode channel is reported in this paper. 1.2 kV SiC MOSFETs with a variety of cell designs were fabricated and compared with respect to the output and transfer characteristics, and blocking behaviors. All the design rules, such as channel length, JFET width, contact openings, gate-to-source overlap, and cell pitch were investigated to clearly provide the quantitative impact on the static performances. 2D-simulation was also conducted to support experimental results. As a result, it turned out that the channel length is the most determining factor for the specific on-resistance, resulting in 0.364 mΩ-cm 2 increase per 0.1 μm increase in the channel length. However, the channel potential is also largely dependent on the channel length such that the leakage current tends to increase with short channel design. The enhanced doping in the JFET region with a current spreading layer (CSL) is essential for achieving a narrower JFET width, which satisfies all static performances, as well as device reliability and ruggedness. Methods to further improve the trade-off characteristics using other design aspects are discussed in this paper.

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