Development of an optimizing compiler for a Fujitsu fixed-point digital signal processor

Abstract

A common design methodology for embedded DSP systems is the integration of one or more digital signal processors (DSPs), program memory, and ASIC circuitry onto a single IC. Consequently, program memory size being limited, the criterion for optimality is that the embedded software must be very dense. We describe the development of an optimizing compiler, based on a retargetable compiler infrastructure, for the Fujitsu Elixir, a fixed-point DSP that is primarily used in cellular telephones. For small DSP benchmark programs (25-90 lines of C code), the average ratio of the size of compiler-generated code to the size of hand-written assembly code is 1.18. For a much larger program (more than 800 lines of C code), the ratio of the size of compiled code to the size of hand-written code is similar ( 1.14).

Programming challenges in network processor deployment

“…In short, they are mainly focused on static analysis to resolve fine-grained latency issues. Examples of DSP compilers are CoSy [1], SPAM [29], RECORD [23], and IBM's e-lite [11]. Compilers targeted at embedded systems [24] and ASIPs, such as CoWare's LISATek [2,31], Chess/Checkers [3,22], Tensilica's XCC [4], and FlexWare [25], specialize on retargetability, code density, power issues, and reliability based on a single processing core.…”