Programming challenges in network processor deployment

Abstract

Programming multi-processor ASIPs, such as network processors, remains an art due to the wide variety of architectures and due to little support for exploring different implementation alternatives. We present a study that implements an IP forwarding router application on two different network processors to better understand the main challenges in programming such multi-processor ASIPs. The goal of this study is to identify the elements central to a successful deployment of such systems based on a detailed profiling of the two architectures. Our results show that inefficient partitioning can impact the throughput by more than 30%; a better arbitration of resources increases the throughput by at least 10%, and localization of computation related to the memories can increase the available bandwidth on internal buses by a factor of two. The main observation of our study is that there is a critical lack of tools and methods that support an integrated approach to partitioning, scheduling and arbitration, and data transfer management for such system implementations.

An ILP Formulation for System-Level Application Mapping on Network Processor Architectures

“…Researchers have conducted design case studies [5][6][7][8] and proposed programming models [9][10][11] for multi-processor and block multi-threaded network processor architectures. However, they have not presented generalized methodologies for programming network processors, much less automated techniques for doing so.…”

FEADS: A Framework for Exploring the Application Design Space on Network Processors

“…(13) An IP forwarding router application was implemented on the IXP1200 and Motorola C-5 network processors. The application was partitioned at the logical cutting points revealed by the application, such as packet receive, header processing, and packet transmit.…”

“…It has been observed that the critical factors in programing network processors are partitioning of tasks onto processors and threads, scheduling of resources, assignment of data to memory elements, and data transfer management. (13) Additionally, other constraints like size of the instruction store and capacities of the memory elements need to be considered during binding of tasks to resources. Further, scheduling multiple instances of the application might yield better throughput than a single instance as will be shown in Section 4.2.2.…”

IP routing processing with graphic processors

“…To improve programmability and re-configurability, today's hardware routers are increasingly using programmable, network processors (NPs) to perform data-plane routing applications such as table lookup, packet classification and deep packet inspection (DPI) [7]. However, NPs are hard to program due to the lack of mature programming models as well as software development tools and incompatibility of architectures [8]. The situation is even worsened by the relatively small size of the developer community for NPs.…”