Development of double-sided with double-chip stacking structure using panel level embedded wafer level packaging

Abstract

In recent years, consumer electronics demand has been geared towards lightweight, high capacity, and high efficiency small form factor devices. These characteristics can be achieved by using three-dimensional (3D) integrated circuit (IC) technology. This study proposes a double-chip stacking structure in an embedded fan-out wafer level packaging (WLP) with double-sided interconnections. This structure consists of two or more thin dies, chip carriers, through mold vias (TMV), and interconnection structures. The thermal performance of the proposed packaging structure is examined and discussed by using finite element (FE) analysis. An FE model of the WLP is also established to compare the thermal performance of conventional WLP and the proposed packaging structure. The proposed packaging structure has a larger size and silicon carrier, which reduces its thermal resistance from 49 °C/W to 39 °C/W. By adopting the proposed design guidelines, including carrier material selection, and designating thermal vias and chip/package size ratios, FE analysis determined that the thermal performance of the proposed packaging structure can be further improved, thereby enhancing its suitability for applications with high power density.