Development of full-HD multi-standard video CODEC IP based on heterogeneous multiprocessor architecture

Abstract

To solve recent pressing issues regarding satisfying numerous video codec standards and supporting "full-high-definition" (full-HD) (i.e., 1920 pixels by 1080 lines) video on different consumer devices, a multi-standard CODEC IP based on a heterogeneous multiprocessor architecture was developed. To achieve satisfactory performance with low power consumption, operation-specific processors were designed in regards to two types of processing: stream processing and pixel processing. The CODEC uses effectively several dedicated circuits for functions which are unsuitable for those processors. To design the CODEC, we developed a C-language model to check that the architecture worked correctly. The model was also used as a reference for verifying the RTL model. The CODEC can process full-HD videos formatted in H.264, MPEG-2, MPEG-4, and VC-1 at an operating frequency of 162 MHz.

A 40 Mbps H.264/AVC CAVLC decoder using a 64-bit multiple-issue video parsing coprocessor

“…Bae et al [2] used a dedicated hardware for parsing each video format. Nakata et al [3] employed a dual-issue VLlW as a syntax parser as well as a hardware accelerator to enhance H.264 CAVLC decoding performance. Lee et al [4] implemented a dual-issue VLlW processor for H.264 CAVLC decoder.…”