Abstract:In this paper, development of single-phase liquid cooling techniques for flip chip ball grid array packages (FBGAs) with high flux heat dissipations is reported. Two thermal test chips with different footprints, 12 mm 12 mm and 10 mm 10 mm, respectively, were used for high heat flux characterizations. A liquid-cooled aluminum heat sink with an area of 15 mm (L) 12.2 mm (W) populated by microchannels was designed and fabricated. The microchannel heat sink was assembled onto the chip, using a thermal interface m… Show more
“…Once assembled, an encapsulant is applied between the die and substrate to seal the interface between the fluidic I/Os and the vias in the substrate (Figure 2.18). This approach is radically different from previously reported research [35,36] in the area of fluidic interconnects for ICs. In order to characterize the fluidic interconnects and the microchannel heat sink and perform temperature measurements, thin-film Pt heaters/thermometers were fabricated on the silicon die.…”
Section: Fluidic I/os For Single and 3d Chipscontrasting
“…Once assembled, an encapsulant is applied between the die and substrate to seal the interface between the fluidic I/Os and the vias in the substrate (Figure 2.18). This approach is radically different from previously reported research [35,36] in the area of fluidic interconnects for ICs. In order to characterize the fluidic interconnects and the microchannel heat sink and perform temperature measurements, thin-film Pt heaters/thermometers were fabricated on the silicon die.…”
Section: Fluidic I/os For Single and 3d Chipscontrasting
“…Since then, microchannel heat sink performance using different substrate materials and channel dimensions have been studied extensively in the past two decades. These studies can be categorized into theoretical [3][4][5][6], numerical [7][8][9][10][11], and experimental approaches [12][13][14][15][16]. In the theoretical approach, the main objective is to develop design schemes that can be used to optimize microchannel heat sink performance.…”
“…Without compromising processing speed, the integration of multi-chips in one interposer on the package tends to generate higher heat density, which needs to be addressed in the 2.5D or 3D package design. [102][103][104][105][106][107][108][109][110][111][112][113][114][115] A schematic of the cooling concepts is illustrated in Figure 50.…”
Section: Thermal Considerations Of 25d Packagesmentioning
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