Development of TSMC 0.25/spl mu/m standard cell library

Djigbenou, Jeannette Donan; Nguyen, Thien Van; Ren, Cheng Wei; Ha, Dong Sam

doi:10.1109/secon.2007.342966

Cited by 3 publications

(2 citation statements)

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“…2(a), was designed and verified by performing PSPICE simulation with supply voltage ± 2.5V using CMOS TSMC 0.25μm technology parameters [21,22]. The CMOS DPDVCC with 4-bit current summing network at port-Z (i.e.…”

Section: Design and Verificationmentioning

confidence: 99%

Reconfigurable fully differential first order all pass filter using digitally controlled CMOS DVCC

Khan

Masud

Моиз

2015

2015 IEEE 8th GCC Conference &Amp; Exhibition

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The paper presents a reconfigurable fully differential all pass filter based on CMOS differential voltage current conveyor. The proposed topology uses two differential voltage current conveyors along with two resistors and two capacitors. The phase angle of the realized fully differential all pass filter can be controlled through an n-bit digital control word. Thus the proposed filter topology provides increased immunity to external noise, reduced even-order harmonics, high resolution capability and reconfigurability. The proposed filter circuit is simulated by using PSPICE. The results thus obtained justify the theory.

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Section: Design and Verificationmentioning

confidence: 99%

Reconfigurable fully differential first order all pass filter using digitally controlled CMOS DVCC

Khan

Masud

Моиз

2015

2015 IEEE 8th GCC Conference &Amp; Exhibition

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“…Standard cell library is a basic and important part of IPs. Traditional design method of standard cells has a complicate design flow [1][2][3] , which is timeconsuming and costly. Migration and reuse technology of layouts have been studied in recent decades [4][5][6][7] .…”

Section: Introductionmentioning

confidence: 99%

A method of automatically tuning gate length and width in a standard cell

Liu

Chen

et al. 2013

2013 Ninth International Conference on Natural Computation (ICNC)

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This paper presents a method of tuning the gate length and width in a standard cell for reuse, which includes the algorithm for auto-identification, obtaining of the gate information and tuning of the locations and/or sizes of the related layout patterns. Existing layouts of standard cells are reused to design new standard cells. Experimental results show that this method can improve the efficiency of standard cell designs and facilitate the generation of standard cells satisfying the requirements of physical optimization.

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