Developments in the fabrication and performance of high-quality HgCdTe detectors grown on 4-in. Si substrates

Inductively coupled plasma etching for large format HgCdTe focal plane array fabrication

“…In addition to the recent data for dry ICP mesa and CdTe passivation etching evaluated here, the figure incorporates 40-µm unitcell median RoA detector data for process variations that include dry ECR mesa etching and standard wet chemical processing. 6 HgCdTe material growth on Si (MBE) and CdZnTe (MBE and LPE) a b substrates is also represented. Work demonstrating MWIR HgCdTe/Si detector performance to be indistinguishable for either ECR dry or wet chemical mesa etching has been described previously by Varesi et al 6 This study confirms a similar result for ICP mesa etching and also shows that ICP dry CdTe passivation etching can be applied as an alternative to wet chemical etching for MWIR HgCdTe/Si detector fabrication.…”

“…and 6-in.-diameter Si wafers. [6][7][8][9] These wafer dimensions diminish requirements for custom wafer handling techniques during wafer processing and provide greater compatibility with standard semiconductor fabrication tooling available to the Si and III-V semiconductor industries. In addition to large format FPA technology, a great number of FPA formats with varied dimensions and configurations can benefit from maturing MBE HgCdTe/Si technology on 4-in.…”

HgCdTe/Si materials for long wavelength infrared detectors

“…(211)Si wafers in a Riber (RueilMalmaison, France) Epineat system using our baseline process described earlier. [7][8][9] The growth is initiated with approximately 1 µm of ZnTe to ensure a (211)B orientation and is followed with a 6-8-µm layer of CdTe, which helps to reduce the propagation of threading dislocations. To maintain a clean growth surface, these substrates were never removed from the MBE system prior to growth of HgCdTe.…”

“…(211)Si substrates. [7][8][9][10] For this technology to be more widely used, it is important to extend these results into the LWIR regime to realize the same benefits of using large-area HgCdTe/Si wafers. Historically, limitations in the performance of LWIR HgCdTe detectors on Si substrates have been attributed to a high dislocation density in the heteroepitaxial HgCdTe 2,5 because dislocations are known to degrade the performance of LWIR HgCdTe detectors, particularly at low temperatures.…”

Realization of very long wavelength infrared photovoltaic detector arrays on mercury cadmium telluride epitaxial layers grown on Si substrates

“…Short wavelength infrared and mid-wavelength infrared detector arrays with state-of-the-art performance levels at 77 K have already been reported in the literature using HgCdTe-on-Si material. [1][2][3][4][5][6][7] However, high dislocation densities in the mid-10 6 cm À2 range in HgCdTe/Si material are proving to be a bottleneck in realizing high-performance uniform arrays operating at 40 K. Current efforts toward reducing dislocation density include (1) using various buffer layers, such as CdTe, CdSeTe, and CdZnTe to terminate the buffer layer growth with lattice-matching conditions for epitaxial HgCdTe growth [8][9][10][11] and (2) bending of dislocations away from the active diode area using dislocation gettering techniques. [12][13][14][15] In addition, control of core charges of dislocations toward higher core charge values in order to enhance the shunt resistance of an individual dislocation has been recently suggested as an alternative method to reduce the contribution of dislocations.…”