Device and circuit-level analog performance trade-offs: a comparative study of planar bulk FETs versus FinFETs

Analog performance of standard and strained triple-gate silicon-on-insulator nFinFETs

“…Additionally to its digital performance, the use of FinFETs in analog applications has also been demonstrated in the literature exhibiting extremely reduced drain output conductance [3,4] and improved analog figures of merit with respect to bulk planar transistors [5,6].…”

Influence of the sidewall crystal orientation, HfSiO nitridation and TiN metal gate thickness on n-MuGFETs under analog operation

“…Moreover, a quasi-ideal subthreshold slope and a better ratio between on-off current were also observed [20][21][22][23][24].…”

Silicon on Insulator Technology Review

“…The unique feature of today's SOI wafers is that they have a buried silicon oxide (Buried Oxide, or BOX) layer extending across the entire wafer, just below a surface layer of device-quality singlecrystal silicon.. At the present time, most SOI wafers are fabricated by use of one of two basic approaches. SOI wafers may be fabricated with the SIMOXTM ( [124,123] Alternately, SOI wafers can be fabricated by bonding a device quality silicon wafer to another silicon wafer (the "handle" wafer) that has an oxide layer on its surface. [145,144] the pair is then split apart, using a process that leaves a thin (relative to the thickness of the starting wafer), device-quality layer of single crystal silicon on top of the oxide layer (which has now become the BOX) on the handle wafer.…”