Device and integration technologies for VLSI in post-Moore era

Abstract

We herein review the technology transition from the scaling-driven technical roadmap to the powerdriven post-Moore roadmap, focusing on the primary trend in micro/nanoelectronics devices. The novel devices and process integration technologies in post-Moore era, such as the FinFET, gate-all-around transistor, tunneling FET, and the sequential 3D integration process were systematically analyzed to provide new insights into the everlasting evolution of VLSI technology.

The Trend of 2D Transistors toward Integrated Circuits: Scaling Down and New Mechanisms

“…A through‐layer via is generally used to achieve 3D transistor‐level stacking in stacked structures. [ 52 ] The space between transistors can reach the scale of local interconnection to greatly improve the efficiency of the transmission lines while reducing delays and power consumption. The challenge for the future is to realize ultrascaled L g and L CH in stacking structures in 2D semiconductors in high‐density circuits such that the transistor footprint is minimized and performance is optimized.…”

Deep learning hardware acceleration based on general vector DSP

“…芯片集成度的提高, 带来了功耗的不断增长. 工艺尺寸不断缩小, 同时一些新的技术 如单片式三维堆叠集成 (TSV) 等 [27] , 对降低功耗有重要作用. [31] 、 可重构数据流处理器 NeuFlow [32] 、 结合 Winograd 算法采用 行缓冲结构实现高效数据复用的 CNN 加速器 [21] 等.…”