Device-, Circuit- &amp; Block-level evaluation of CFET in a 4 track library

Schuddinck, P.; Zografos, Odysseas; Weckx, Pieter; Matagne, P.; Sarkar, Santonu; Sherazi, Yasser; Baert, Rogier; Jang, Doyoung; Yakimets, D.; Gupta, Anshul; Parvais, B.; Ryckaert, Julien; Verkest, D.; Mocuta, A.

doi:10.23919/vlsit.2019.8776513

Cited by 47 publications

(19 citation statements)

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“…As a single fin was used, the inverter area decreased greatly by 53 % compared to 2-fin SDP FinFETs. CMOS inverter area of complementary FETs (CFETs) is also shown for comparison [8]. Among all, the 1-fin SDP FinFETs occupy the smallest inverter area.…”

Section: Resultsmentioning

confidence: 99%

“…8). Interconnect resistance and capacitance per wire length are from [7], [9], and wire length was simply assumed as 25×CPP+3.33×CH, where the CH is a cell height as 2×(SP+FP) [8]. Conventional FinFETs in three different technology nodes have similar circuit performances, but the device area is shrunk by decreasing CPP and FP.…”

Section: Resultsmentioning

confidence: 99%

“…Table 1 shows the geometrical parameters and values of all the FinFETs. The CPP and FP for each technology nodes are referred from [1], [8] and [9]. Gate length (L g ) and spacer length (L sp ) were scaled down to 12 and 5 nm in the 5-nm node, respectively [15].…”

Section: Device Structure and Simulation Methodsmentioning

confidence: 99%

“…the short channel effects (SCEs) and decreases the gate capacitances (C gg ) due to the small S/D epi. However, some novel process scheme is still required to scale down the device area, limited in scaling by the minimum features of the contacted poly-pitch (CPP) of 42 nm and fin pitch (FP) of 21 nm by self-aligned quadruple patterning [8]. Large S/D epi formed by selective epitaxial growth (SEG) also constrains the scaling of FinFETs due to the risk of epi merging [9].…”

Section: Introductionmentioning

confidence: 99%

“…CMOS Inverter area of all the FinFETs. The area of complementary FETs was also included for comparison[8].…”

mentioning

confidence: 99%

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Source/Drain Patterning FinFETs as Solution for Physical Area Scaling Toward 5-nm Node

Yoon

Lee

et al. 2019

IEEE Access

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A novel and feasible process scheme to downsize the source/drain (S/D) epitaxy of 5-nm node bulk fin-shaped field-effect transistors (FinFETs) were introduced by using fully-calibrated TCAD for the first time. The S/D epitaxy formed by selective epitaxial growth was diamond-shaped and occupied a large proportion of the device size irrespective of the active channel area. However, this problem was solved by patterning the low-k regions prior to S/D formation by preventing the lateral overgrowth of S/D epitaxy; the so-called S/D patterning (SDP). Its smaller S/D epitaxy decreased the average longitudinal channel stresses and drive currents for NFETs. However, the small diffusions of the boron dopants into the channel regions improved the short-channel effects and alleviated the drive current reduction for PFETs. Gate capacitances decreased greatly by reducing outer-fringing capacitances between the metal-gate stack and S/D regions. Through SPICE simulation based on the virtual source model, operation frequencies and dynamic powers of 15-stage ring oscillators were studied. SDP FinFETs have better circuit performances than the conventional and bottom oxide bulk FinFETs along with smaller active areas, promising for further area scaling through simple and reliable S/D process.

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Section: Resultsmentioning

confidence: 99%