Device dependence of charging effects from high-current ion implantation

Reduction of RIE-damage by N/sub 2/O-anneal of thermal gate oxide

“…Examples of such processes include polysilicon etch, contact and via formation, multiple metal etches, various photoresist strips, etc. Some charging damage has also been reported during ion implant steps [17]. Since N O oxides are known to have an improved robustness than thermal oxides under various stress conditions, an obvious question to ask is whether these oxides have better immunity against plasma charging related damage.…”

“…In addition, these oxides have a key benefit that they can be easily integrated in a conventional CMOS process flow. Among various factors which dictate the choice of a gate dielectric for a scaled process, plasma induced damage has gained a lot of attention in recent years [11]- [17]. Various plasma based dry etch processes, which become necessary for defining small feature sizes, can result in tunnel current flow through thin gate dielectrics, thereby degrading them [12], [13].…”

Wafer Charging Control in High‐Current Implanters

“…In these applications, the very high rate of charge deposition and induced charges on the surface of 4-8 in. diam wafers can cause serious damage to the wafers and the devices or circuits on them, ranging from macroscopic poor implant dose uniformity (2) to microscopic deterioration of individual devices (1,5). The macrocharging effect is caused by charging of the entire wafer surface, leading to changes in the ion beam profile at the wafer plane and results in a nonuniform implant, generally characterized by a low dose at the center of the wafer and a high dose near the edges.…”